All Stories

  1. Randomized processes to create diverse models for One-class classifier ensembles
  2. RelOps: Reliability Optimization in Standard Cells across PVT Variations in FinFET Digital Circuits
  3. AI-Assisted Circuit Design and Modeling
  4. Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation
  5. A label-free sensing of creatinine using radio frequency-driven lab-on-chip (loc) system
  6. A 275 pW, 0.5 V supply insensitive gate-leakage based current/voltage reference circuit for a wide temperature range of −55 to 100 °C without using amplifiers and resistors
  7. Qualitative data augmentation for performance prediction in VLSI circuits
  8. A Theoretical Study of the Representational Power of Weighted Randomised Univariate Regression Tree Ensembles
  9. AI/ML algorithms and applications in VLSI design and technology
  10. Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture
  11. A Novel Smart Belt for Anxiety Detection, Classification, and Reduction Using IIoMT on Students’ Cardiac Signal and MSY
  12. An End-to-End Cardiac Arrhythmia Recognition Method with an Effective DenseNet Model on Imbalanced Datasets Using ECG Signal
  13. A 9.5nW, 0.55V Supply, CMOS Current Reference for Low Power Biomedical Applications
  14. Implementation of TRNG with SHA-3 for hardware security
  15. A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems
  16. Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence
  17. Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations
  18. PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits
  19. Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence
  20. ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications
  21. An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells
  22. Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance
  23. 67ppm/°C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications
  24. A Sub-nW, 8T Current Reference Consuming Constant Power w.r.t Process & Temperature
  25. A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator
  26. 3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications
  27. Optimal Power-Area Polar Decoder Design based on Iterative Decomposition Technique
  28. A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits
  29. A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design
  30. A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications
  31. A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications
  32. PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design
  33. Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms
  34. LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits
  35. Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power
  36. Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models
  37. Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier
  38. Geometry Scaling Impact on Leakage Currents in FinFET Standard Cells Based on a Logic-Level Leakage Estimation Technique
  39. THERMAL STUDY OF LAB ON CHIP (LOC) SYSTEM FOR PCR REACTION APPLICATIONS
  40. Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations
  41. MS 16 MINISYMPOSIUM: METHODS FOR ADVANCED MULTI-OBJECTIVE OPTIMIZATION FOR eDFY OF COMPLEX NANO-SCALE CIRCUITS
  42. Statistical Variation Aware ANN and SVM Model Generation for Digital Standard Cells
  43. Optimal transistor sizing for maximum yield in variation-aware standard cell design
  44. Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell
  45. Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions
  46. A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs
  47. Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
  48. Sizing and optimization of low power process variation aware standard cells
  49. Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)
  50. Yield optimization for low power current controlled current conveyor
  51. A novel logic level calculation model for leakage currents in digital nano-CMOS circuits
  52. Experimental use of electronic nose for analysis of volatile organic compound (VOC)