All Stories

  1. A CSRR-IDC-Based Microwave Biosensor for Non-invasive Creatinine Detection
  2. Randomized processes to create diverse models for One-class classifier ensembles
  3. RelOps: Reliability Optimization in Standard Cells across PVT Variations in FinFET Digital Circuits
  4. AI-Assisted Circuit Design and Modeling
  5. Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation
  6. A label-free sensing of creatinine using radio frequency-driven lab-on-chip (loc) system
  7. A 275 pW, 0.5 V supply insensitive gate-leakage based current/voltage reference circuit for a wide temperature range of −55 to 100 °C without using amplifiers and resistors
  8. Qualitative data augmentation for performance prediction in VLSI circuits
  9. A Theoretical Study of the Representational Power of Weighted Randomised Univariate Regression Tree Ensembles
  10. AI/ML algorithms and applications in VLSI design and technology
  11. Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture
  12. A Novel Smart Belt for Anxiety Detection, Classification, and Reduction Using IIoMT on Students’ Cardiac Signal and MSY
  13. An End-to-End Cardiac Arrhythmia Recognition Method with an Effective DenseNet Model on Imbalanced Datasets Using ECG Signal
  14. A 9.5nW, 0.55V Supply, CMOS Current Reference for Low Power Biomedical Applications
  15. Implementation of TRNG with SHA-3 for hardware security
  16. A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems
  17. Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence
  18. Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations
  19. PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits
  20. Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence
  21. ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications
  22. An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells
  23. Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance
  24. 67ppm/°C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications
  25. A Sub-nW, 8T Current Reference Consuming Constant Power w.r.t Process & Temperature
  26. A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator
  27. 3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications
  28. Optimal Power-Area Polar Decoder Design based on Iterative Decomposition Technique
  29. A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits
  30. A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design
  31. A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications
  32. A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications
  33. PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design
  34. Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms
  35. LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits
  36. Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power
  37. Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models
  38. Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier
  39. Geometry Scaling Impact on Leakage Currents in FinFET Standard Cells Based on a Logic-Level Leakage Estimation Technique
  40. THERMAL STUDY OF LAB ON CHIP (LOC) SYSTEM FOR PCR REACTION APPLICATIONS
  41. Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations
  42. MS 16 MINISYMPOSIUM: METHODS FOR ADVANCED MULTI-OBJECTIVE OPTIMIZATION FOR eDFY OF COMPLEX NANO-SCALE CIRCUITS
  43. Statistical Variation Aware ANN and SVM Model Generation for Digital Standard Cells
  44. Optimal transistor sizing for maximum yield in variation-aware standard cell design
  45. Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell
  46. Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions
  47. A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs
  48. Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
  49. Sizing and optimization of low power process variation aware standard cells
  50. Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)
  51. Yield optimization for low power current controlled current conveyor
  52. A novel logic level calculation model for leakage currents in digital nano-CMOS circuits
  53. Experimental use of electronic nose for analysis of volatile organic compound (VOC)