All Stories

  1. Strix: Re-thinking NPU Reliability from a System Perspective
  2. UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
  3. LLMVA: LLMs Empowered Verilog-A Iterative for MRAM Design Technology Co-Optimization
  4. ChipModeler: LLM-Aided Reference Model Design for Agile Hardware Verification
  5. From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
  6. Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
  7. MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
  8. System Optimization for Coarse-Grained Reconfigurable Arrays
  9. Thetis-lathe: Guidance on Reducing Residual Safety Obstacle in System Software from Rust Source Codes
  10. NVR: Vector Runahead on NPUs for Sparse Memory Access
  11. BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language Models
  12. Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
  13. Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
  14. Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
  15. Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors
  16. MEIC: Re-thinking RTL Debug Automation using LLMs
  17. A Cache/Algorithm Co-design for Parallel Real-Time Systems with Data Dependency on Multi/Many-core System-on-Chips
  18. Many-Core Real-Time Network-on-Chip I/O Systems for Reducing Contention and Enhancing Predictability
  19. Designing critical systems with iterative automated safety analysis