All Stories

  1. MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
  2. System Optimization for Coarse-Grained Reconfigurable Arrays
  3. Thetis-lathe: Guidance on Reducing Residual Safety Obstacle in System Software from Rust Source Codes
  4. NVR: Vector Runahead on NPUs for Sparse Memory Access
  5. BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language Models
  6. Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
  7. Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
  8. Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
  9. Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors
  10. MEIC: Re-thinking RTL Debug Automation using LLMs
  11. A Cache/Algorithm Co-design for Parallel Real-Time Systems with Data Dependency on Multi/Many-core System-on-Chips
  12. Many-Core Real-Time Network-on-Chip I/O Systems for Reducing Contention and Enhancing Predictability
  13. Designing critical systems with iterative automated safety analysis