All Stories

  1. VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
  2. An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
  3. An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA
  4. Low-cost stochastic number generator based on MRAM for stochastic computing
  5. HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation
  6. High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features
  7. Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme
  8. An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits
  9. Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy
  10. DNN Intellectual Property Protection
  11. Approximate Computing: From Circuits to Applications
  12. Hybrid Low Radix Encoding-Based Approximate Booth Multipliers
  13. Design, evaluation and application of approximate-truncated Booth multipliers
  14. High Performance Modular Multiplication for SIDH
  15. Security Analysis of Hardware Trojans on Approximate Circuits
  16. AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication
  17. Dither-based calibration of bit weights in pipelined-SAR ADCs with fast convergence speed using partially split structure
  18. Embedding Backdoors as the Facial Features
  19. Lightweight Modeling Attack-Resistant Multiplexer-Based Multi-PUF (MMPUF) Design on FPGA
  20. An Efficient and Parallel R-LWE Cryptoprocessor
  21. Guest Editorial: Introduction to the Special Section on Cyber Security Threats and Defense Advance
  22. A Retrospective and Prospective View of Approximate Computing [Point of View}
  23. Attenuation-factor error shaping technique for split CDAC in SAR ADCs
  24. DPAEG: A Dependency Parse-Based Adversarial Examples Generation Method for Intelligent Q&A Robots
  25. Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators
  26. Machine Learning Security: Threats, Countermeasures, and Evaluations
  27. Profile-Based Output Error Compensation for Approximate Arithmetic Circuits
  28. Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3
  29. High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization
  30. Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities
  31. Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits
  32. Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman
  33. New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata
  34. Design and Analysis of Approximate Redundant Binary Multipliers
  35. XOR-Based Low-Cost Reconfigurable PUFs for IoT Security
  36. Building an Accurate Hardware Trojan Detection Technique from Inaccurate Simulation Models and Unlabeled ICs
  37. A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations
  38. Defeating Untrustworthy Testing Parties: A Novel Hybrid Clustering Ensemble Based Golden Models-Free Hardware Trojan Detection Method
  39. Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA
  40. Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition
  41. Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications
  42. Design, Evaluation and Application of Approximate High-Radix Dividers
  43. Data Compression Device Based on Modified LZ4 Algorithm
  44. Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design
  45. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
  46. Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications
  47. Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
  48. Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)
  49. Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders
  50. Design and Analysis of Inexact Floating-Point Adders
  51. Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing