All Stories

  1. High-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT
  2. A Highly Reliable Dual-Mode RRAM PUF With Key Concealment Scheme
  3. A 0.071pJ/Bit Flexible Multi-Mode Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF
  4. A Dual-Swing-Sample-and-Couple Sense Amplifier With Large Sensing Margin for STT-MRAM
  5. A Novel Error Metric for Evaluating the Error Correction Capability of Approximate Units
  6. Two Low-Cost and Security-Enhanced Implementations Against Side-Channel Attacks of NTT for Lattice-Based Cryptography
  7. HDANNS: In-Memory Hyperdimensional Computing for Billion-Scale Approximate Nearest Neighbour Search Acceleration
  8. MRAM-Based Cache and In-Memory Computing
  9. An Efficient Methodology for Binary Logarithmic Computations of Floating-Point Numbers With Normalized Output Within One ulp of Accuracy
  10. Temperature-Adaptive TRNG-Encrypted MRAM PUF: Enhancing Resistance to Machine Learning Attacks
  11. Instruction-Based High-Performance Hardware Controller of CRYSTALS-Kyber With Balanced Resource Utilization
  12. Low-Cost Yet Effective Trojan Mitigation Techniques for Approximate Systems
  13. High-Radix Generalized Hyperbolic CORDIC and Its Hardware Implementation
  14. A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications
  15. A High-Speed and High-Yield Path-Switching Sensing Circuit for STT-MRAM
  16. Comparison of Single-Event Transient Under Heavy Ion and Pulsed Laser Irradiation in SiGe HBT Ultrawideband LNA
  17. LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator
  18. 3D Invisible Cloak: A Robust Person Stealth Attack Against Object Detector in Complex 3D Physical Scenarios
  19. A Low-Power and Reliable RRAM-Based Configurable RO PUF With Aging Resilience
  20. A Multi-Mode Configurable Physical Unclonable Function Based on RRAM With Adjustable Programmable Voltage
  21. An Active Authorization Control Method for Deep Reinforcement Learning Model Based on GANs and Adaptive Trigger
  22. Energy Efficient Approximate Computing Framework for DNN Acceleration Using a Probabilistic-Oriented Method
  23. High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms
  24. SS-MRAM: A Segment-Based Search Scheme With Configurable Matching for High-Accuracy Hyperdimensional Computing in CAM Applications
  25. Dynamic Challenge Cross-Selection Physical Unclonable Function Based on MRAM
  26. E2CAP: An Energy-Efficient FPGA Accelerator for Deep Reinforcement Learning With Experience Compression and Configurable PE Array
  27. ACIMC: A 342.7-TOPS/mm 2 eDRAM-Based Analog Cryogenic In-Memory Computing Macro
  28. A Highly Hardware Efficient ML-KEM Accelerator with Optimised Architectural Layers
  29. A Reinforcement Learning-Based ELF Adversarial Malicious Sample Generation Method
  30. AttnACQ: Attentioned-AutoCorrelation-Based Query for Hyperdimensional Associative Memory
  31. Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication
  32. Memristor-Based Approximate Query Architecture for In-Memory Hyperdimensional Computing
  33. A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices
  34. Guest Editorial: Special Section on “Approximate Data Processing: Computing, Storage and Applications”
  35. An Explainable Intellectual Property Protection Method for Deep Neural Networks Based on Intrinsic Features
  36. SSAT: Active Authorization Control and User’s Fingerprint Tracking Framework for DNN IP Protection
  37. Progressive Approximation-Aware Training with Regularization and Transfer Learning for DNN Acceleration
  38. An Imperceptible and Owner-unique Watermarking Method for Graph Neural Networks
  39. Tracking the Leaker: An Encodable Watermarking Method for Dataset Intellectual Property Protection
  40. A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM
  41. FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations
  42. Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application
  43. Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization
  44. Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme
  45. Untargeted Backdoor Attack Against Deep Neural Networks With Imperceptible Trigger
  46. Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications
  47. VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits
  48. VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
  49. An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
  50. HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining
  51. An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA
  52. Design of High Hardware Efficiency Approximate Floating-Point FFT Processor
  53. High-Throughput Polynomial Multiplier for Accelerating Saber on FPGA
  54. AdvParams: An Active DNN Intellectual Property Protection Technique via Adversarial Perturbation Based Parameter Encryption
  55. Detecting backdoor in deep neural networks via intentional adversarial perturbations
  56. Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS
  57. MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM
  58. ActiveGuard: An active intellectual property protection technique for deep neural networks by leveraging adversarial examples as users' fingerprints
  59. ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations
  60. An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs
  61. Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing
  62. Security and Approximation: Vulnerabilities in Approximation-Aware Testing
  63. Use the Spear as a Shield: An Adversarial Example Based Privacy-Preserving Technique Against Membership Inference Attacks
  64. Approximate Softmax Functions for Energy-Efficient Deep Neural Networks
  65. A 3.8-μW 10-Keyword Noise-Robust Keyword Spotting Processor Using Symmetric Compressed Ternary-Weight Neural Networks
  66. A Survey of Majority Logic Designs in Emerging Nanotechnologies for Computing
  67. High-Performance STT-MRAM-Based Computing-in-Memory Scheme Utilizing Data Read Feature
  68. Low-cost stochastic number generator based on MRAM for stochastic computing
  69. HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation
  70. High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features
  71. Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme
  72. Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits
  73. Intellectual Property Protection for Deep Learning Models: Taxonomy, Methods, Attacks, and Evaluations
  74. Deep Learning-Based Hardware Trojan Detection With Block-Based Netlist Information Extraction
  75. Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs
  76. A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs
  77. A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product
  78. GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy
  79. AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications
  80. Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms
  81. An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits
  82. Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy
  83. A High-Performance SIKE Hardware Accelerator
  84. One-to-N & N-to-One: Two Advanced Backdoor Attacks Against Deep Learning Models
  85. More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network
  86. Design and analysis of energy‐efficient approximate Booth‐folding squarers with precision recovery
  87. Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers
  88. Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers
  89. A Fully Configurable PUF Using Dynamic Variations of Resistive Crossbar Arrays
  90. Design of Majority Logic-Based Approximate Booth Multipliers for Error-Tolerant Applications
  91. Exact and Approximate Squarers for Error-Tolerant Applications
  92. Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation
  93. Design and analysis of hardware Trojans in approximate circuits
  94. An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering
  95. A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation
  96. Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning
  97. Reduced Precision Redundancy for Reliable Processing of Data
  98. Stochastic Dividers for Low Latency Neural Networks
  99. A Real-Time Hardware Emulator for 3D Non-Stationary U2V Channels
  100. An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity
  101. Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers
  102. DNN Intellectual Property Protection
  103. A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication
  104. BCD Adder Designs Based on Three-Input XOR and Majority Gates
  105. Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows
  106. AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators
  107. A Hardware/Software Co-Design Methodology for Adaptive Approximate Computing in clustering and ANN Learning
  108. A Physical Unclonable Function Using a Configurable Tristate Hybrid Scheme With Non-Volatile Memory
  109. APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations
  110. Approximate Computing: From Circuits to Applications
  111. Hybrid Low Radix Encoding-Based Approximate Booth Multipliers
  112. Mathematical Modeling Analysis of Strong Physical Unclonable Functions
  113. Design, evaluation and application of approximate-truncated Booth multipliers
  114. High Performance Modular Multiplication for SIDH
  115. Security Analysis of Hardware Trojans on Approximate Circuits
  116. AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication
  117. Dither-based calibration of bit weights in pipelined-SAR ADCs with fast convergence speed using partially split structure
  118. Embedding Backdoors as the Facial Features
  119. Lightweight Modeling Attack-Resistant Multiplexer-Based Multi-PUF (MMPUF) Design on FPGA
  120. An Efficient and Parallel R-LWE Cryptoprocessor
  121. Guest Editorial: Introduction to the Special Section on Cyber Security Threats and Defense Advance
  122. A Retrospective and Prospective View of Approximate Computing [Point of View}
  123. Attenuation-factor error shaping technique for split CDAC in SAR ADCs
  124. DPAEG: A Dependency Parse-Based Adversarial Examples Generation Method for Intelligent Q&A Robots
  125. Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators
  126. Machine Learning Security: Threats, Countermeasures, and Evaluations
  127. Profile-Based Output Error Compensation for Approximate Arithmetic Circuits
  128. Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3
  129. High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization
  130. Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities
  131. Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits
  132. Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman
  133. New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata
  134. Design and Analysis of Approximate Redundant Binary Multipliers
  135. XOR-Based Low-Cost Reconfigurable PUFs for IoT Security
  136. Building an Accurate Hardware Trojan Detection Technique from Inaccurate Simulation Models and Unlabeled ICs
  137. A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations
  138. Defeating Untrustworthy Testing Parties: A Novel Hybrid Clustering Ensemble Based Golden Models-Free Hardware Trojan Detection Method
  139. Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA
  140. Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition
  141. Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications
  142. Design, Evaluation and Application of Approximate High-Radix Dividers
  143. Design of Dynamic Range Approximate Logarithmic Multipliers
  144. Data Compression Device Based on Modified LZ4 Algorithm
  145. Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design
  146. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
  147. Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications
  148. Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
  149. Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)
  150. Design of Approximate Logarithmic Multipliers
  151. Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition
  152. Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders
  153. Design and Analysis of Inexact Floating-Point Adders
  154. Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing