All Stories

  1. Making SPHINCS+ post-quantum signatures faster with efficient hardware
  2. A Methodology for Pre-Silicon Optimization of Processor Based PUF in Approximate Computing
  3. Optimized NTT Architecture Based on the Plantard Algorithm for ML-KEM and ML-DSA
  4. LightHD: A Lightweight and High-Performance Hardware Accelerator of CRYSTALS-Dilithium
  5. Instant-CIM: An Instant Neural Radiance Field Computing-In-Memory Architecture for Low-Power and Real-Time AR/VR Rendering
  6. FPGA-Based Low-Power Signed Approximate Multipliers for Diverse Error-Resilient Applications
  7. A High-Accuracy MRAM-Based Computing-in-Memory Macro for Secure Edge AI Inference
  8. A Lightweight Design of True Random Number Generator Based on Superparamagnetic Tunnel Junction
  9. Approximate Computing-Based Framework for Low-Cost Runtime Hardware Trojan Defense
  10. CT-LNN: FPGA-Based Accelerator for Continuous-Time Liquid Neural Networks
  11. Content-Aware Adaptive Approximate Compression for Energy-Efficient JPEG Enhancement
  12. Neuromorphic Hyperdimensional Computing for Efficiently Processing Event-Based Data
  13. RLDALS: Reinforcement Learning-Guided Domain-Specific Language Model Framework for Approximate Logic Synthesis
  14. A 250-Mb/s On-Chip Capacitive Digital Isolator With 200 kV/ μ s Common-Mode Transient Immunity
  15. High-Precision Low-Latency Method and Architecture for Softmax Acceleration in Training-Level AI Applications
  16. BitSplat: An Efficient 3D Gaussian Splatting Architecture via Bit-Level Hardware-Algorithm Co-Optimization
  17. High-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT
  18. A Highly Reliable Dual-Mode RRAM PUF With Key Concealment Scheme
  19. A 0.071pJ/Bit Flexible Multi-Mode Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF
  20. A Dual-Swing-Sample-and-Couple Sense Amplifier With Large Sensing Margin for STT-MRAM
  21. A Novel Error Metric for Evaluating the Error Correction Capability of Approximate Units
  22. Two Low-Cost and Security-Enhanced Implementations Against Side-Channel Attacks of NTT for Lattice-Based Cryptography
  23. HDANNS: In-Memory Hyperdimensional Computing for Billion-Scale Approximate Nearest Neighbour Search Acceleration
  24. MRAM-Based Cache and In-Memory Computing
  25. An Efficient Methodology for Binary Logarithmic Computations of Floating-Point Numbers With Normalized Output Within One ulp of Accuracy
  26. Temperature-Adaptive TRNG-Encrypted MRAM PUF: Enhancing Resistance to Machine Learning Attacks
  27. Instruction-Based High-Performance Hardware Controller of CRYSTALS-Kyber With Balanced Resource Utilization
  28. Low-Cost Yet Effective Trojan Mitigation Techniques for Approximate Systems
  29. High-Radix Generalized Hyperbolic CORDIC and Its Hardware Implementation
  30. A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications
  31. A High-Speed and High-Yield Path-Switching Sensing Circuit for STT-MRAM
  32. Comparison of Single-Event Transient Under Heavy Ion and Pulsed Laser Irradiation in SiGe HBT Ultrawideband LNA
  33. LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator
  34. 3D Invisible Cloak: A Robust Person Stealth Attack Against Object Detector in Complex 3D Physical Scenarios
  35. A Low-Power and Reliable RRAM-Based Configurable RO PUF With Aging Resilience
  36. A Multi-Mode Configurable Physical Unclonable Function Based on RRAM With Adjustable Programmable Voltage
  37. An Active Authorization Control Method for Deep Reinforcement Learning Model Based on GANs and Adaptive Trigger
  38. Energy Efficient Approximate Computing Framework for DNN Acceleration Using a Probabilistic-Oriented Method
  39. High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms
  40. SS-MRAM: A Segment-Based Search Scheme With Configurable Matching for High-Accuracy Hyperdimensional Computing in CAM Applications
  41. Dynamic Challenge Cross-Selection Physical Unclonable Function Based on MRAM
  42. E2CAP: An Energy-Efficient FPGA Accelerator for Deep Reinforcement Learning With Experience Compression and Configurable PE Array
  43. ACIMC: A 342.7-TOPS/mm 2 eDRAM-Based Analog Cryogenic In-Memory Computing Macro
  44. A Highly Hardware Efficient ML-KEM Accelerator with Optimised Architectural Layers
  45. A Reinforcement Learning-Based ELF Adversarial Malicious Sample Generation Method
  46. AttnACQ: Attentioned-AutoCorrelation-Based Query for Hyperdimensional Associative Memory
  47. Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication
  48. Memristor-Based Approximate Query Architecture for In-Memory Hyperdimensional Computing
  49. A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices
  50. Guest Editorial: Special Section on “Approximate Data Processing: Computing, Storage and Applications”
  51. An Explainable Intellectual Property Protection Method for Deep Neural Networks Based on Intrinsic Features
  52. SSAT: Active Authorization Control and User’s Fingerprint Tracking Framework for DNN IP Protection
  53. Progressive Approximation-Aware Training with Regularization and Transfer Learning for DNN Acceleration
  54. An Imperceptible and Owner-unique Watermarking Method for Graph Neural Networks
  55. Tracking the Leaker: An Encodable Watermarking Method for Dataset Intellectual Property Protection
  56. A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM
  57. FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations
  58. Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application
  59. Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization
  60. Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme
  61. Untargeted Backdoor Attack Against Deep Neural Networks With Imperceptible Trigger
  62. Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications
  63. VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits
  64. VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
  65. An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
  66. HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining
  67. An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA
  68. Design of High Hardware Efficiency Approximate Floating-Point FFT Processor
  69. High-Throughput Polynomial Multiplier for Accelerating Saber on FPGA
  70. AdvParams: An Active DNN Intellectual Property Protection Technique via Adversarial Perturbation Based Parameter Encryption
  71. Detecting backdoor in deep neural networks via intentional adversarial perturbations
  72. Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS
  73. MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM
  74. ActiveGuard: An active intellectual property protection technique for deep neural networks by leveraging adversarial examples as users' fingerprints
  75. ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations
  76. An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs
  77. Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing
  78. Security and Approximation: Vulnerabilities in Approximation-Aware Testing
  79. Use the Spear as a Shield: An Adversarial Example Based Privacy-Preserving Technique Against Membership Inference Attacks
  80. Approximate Softmax Functions for Energy-Efficient Deep Neural Networks
  81. A 3.8-μW 10-Keyword Noise-Robust Keyword Spotting Processor Using Symmetric Compressed Ternary-Weight Neural Networks
  82. A Survey of Majority Logic Designs in Emerging Nanotechnologies for Computing
  83. High-Performance STT-MRAM-Based Computing-in-Memory Scheme Utilizing Data Read Feature
  84. Low-cost stochastic number generator based on MRAM for stochastic computing
  85. HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation
  86. High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features
  87. Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme
  88. Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits
  89. Intellectual Property Protection for Deep Learning Models: Taxonomy, Methods, Attacks, and Evaluations
  90. Deep Learning-Based Hardware Trojan Detection With Block-Based Netlist Information Extraction
  91. Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs
  92. A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs
  93. A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product
  94. GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy
  95. AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications
  96. Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms
  97. An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits
  98. Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy
  99. A High-Performance SIKE Hardware Accelerator
  100. One-to-N & N-to-One: Two Advanced Backdoor Attacks Against Deep Learning Models
  101. More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network
  102. Design and analysis of energy‐efficient approximate Booth‐folding squarers with precision recovery
  103. Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers
  104. Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers
  105. A Fully Configurable PUF Using Dynamic Variations of Resistive Crossbar Arrays
  106. Design of Majority Logic-Based Approximate Booth Multipliers for Error-Tolerant Applications
  107. Exact and Approximate Squarers for Error-Tolerant Applications
  108. Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation
  109. Design and analysis of hardware Trojans in approximate circuits
  110. An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering
  111. A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation
  112. Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning
  113. Reduced Precision Redundancy for Reliable Processing of Data
  114. Stochastic Dividers for Low Latency Neural Networks
  115. A Real-Time Hardware Emulator for 3D Non-Stationary U2V Channels
  116. An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity
  117. Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers
  118. DNN Intellectual Property Protection
  119. A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication
  120. BCD Adder Designs Based on Three-Input XOR and Majority Gates
  121. Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows
  122. AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators
  123. Stochastic Dividers for Low Latency Neural Networks
  124. A Hardware/Software Co-Design Methodology for Adaptive Approximate Computing in clustering and ANN Learning
  125. A Physical Unclonable Function Using a Configurable Tristate Hybrid Scheme With Non-Volatile Memory
  126. APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations
  127. Approximate Computing: From Circuits to Applications
  128. Hybrid Low Radix Encoding-Based Approximate Booth Multipliers
  129. Mathematical Modeling Analysis of Strong Physical Unclonable Functions
  130. Design, evaluation and application of approximate-truncated Booth multipliers
  131. High Performance Modular Multiplication for SIDH
  132. Security Analysis of Hardware Trojans on Approximate Circuits
  133. AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication
  134. Dither-based calibration of bit weights in pipelined-SAR ADCs with fast convergence speed using partially split structure
  135. Embedding Backdoors as the Facial Features
  136. Lightweight Modeling Attack-Resistant Multiplexer-Based Multi-PUF (MMPUF) Design on FPGA
  137. An Efficient and Parallel R-LWE Cryptoprocessor
  138. Guest Editorial: Introduction to the Special Section on Cyber Security Threats and Defense Advance
  139. A Retrospective and Prospective View of Approximate Computing [Point of View}
  140. Attenuation-factor error shaping technique for split CDAC in SAR ADCs
  141. DPAEG: A Dependency Parse-Based Adversarial Examples Generation Method for Intelligent Q&A Robots
  142. Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators
  143. Machine Learning Security: Threats, Countermeasures, and Evaluations
  144. Profile-Based Output Error Compensation for Approximate Arithmetic Circuits
  145. Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3
  146. High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization
  147. Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities
  148. Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits
  149. Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman
  150. New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata
  151. Design and Analysis of Approximate Redundant Binary Multipliers
  152. XOR-Based Low-Cost Reconfigurable PUFs for IoT Security
  153. Building an Accurate Hardware Trojan Detection Technique from Inaccurate Simulation Models and Unlabeled ICs
  154. A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations
  155. Defeating Untrustworthy Testing Parties: A Novel Hybrid Clustering Ensemble Based Golden Models-Free Hardware Trojan Detection Method
  156. Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA
  157. Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition
  158. Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications
  159. Design, Evaluation and Application of Approximate High-Radix Dividers
  160. Design of Dynamic Range Approximate Logarithmic Multipliers
  161. Data Compression Device Based on Modified LZ4 Algorithm
  162. Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design
  163. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
  164. Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications
  165. Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
  166. Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)
  167. Design of Approximate Logarithmic Multipliers
  168. Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition
  169. Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders
  170. Design and Analysis of Inexact Floating-Point Adders
  171. Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing