All Stories

  1. Instant-CIM: An Instant Neural Radiance Field Computing-In-Memory Architecture for Low-Power and Real-Time AR/VR Rendering
  2. FPGA-Based Low-Power Signed Approximate Multipliers for Diverse Error-Resilient Applications
  3. A High-Accuracy MRAM-Based Computing-in-Memory Macro for Secure Edge AI Inference
  4. High-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT
  5. A Highly Reliable Dual-Mode RRAM PUF With Key Concealment Scheme
  6. A 0.071pJ/Bit Flexible Multi-Mode Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF
  7. A Dual-Swing-Sample-and-Couple Sense Amplifier With Large Sensing Margin for STT-MRAM
  8. A Novel Error Metric for Evaluating the Error Correction Capability of Approximate Units
  9. Two Low-Cost and Security-Enhanced Implementations Against Side-Channel Attacks of NTT for Lattice-Based Cryptography
  10. HDANNS: In-Memory Hyperdimensional Computing for Billion-Scale Approximate Nearest Neighbour Search Acceleration
  11. MRAM-Based Cache and In-Memory Computing
  12. An Efficient Methodology for Binary Logarithmic Computations of Floating-Point Numbers With Normalized Output Within One ulp of Accuracy
  13. Temperature-Adaptive TRNG-Encrypted MRAM PUF: Enhancing Resistance to Machine Learning Attacks
  14. Instruction-Based High-Performance Hardware Controller of CRYSTALS-Kyber With Balanced Resource Utilization
  15. Low-Cost Yet Effective Trojan Mitigation Techniques for Approximate Systems
  16. High-Radix Generalized Hyperbolic CORDIC and Its Hardware Implementation
  17. A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications
  18. A High-Speed and High-Yield Path-Switching Sensing Circuit for STT-MRAM
  19. Comparison of Single-Event Transient Under Heavy Ion and Pulsed Laser Irradiation in SiGe HBT Ultrawideband LNA
  20. LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator
  21. 3D Invisible Cloak: A Robust Person Stealth Attack Against Object Detector in Complex 3D Physical Scenarios
  22. A Low-Power and Reliable RRAM-Based Configurable RO PUF With Aging Resilience
  23. A Multi-Mode Configurable Physical Unclonable Function Based on RRAM With Adjustable Programmable Voltage
  24. An Active Authorization Control Method for Deep Reinforcement Learning Model Based on GANs and Adaptive Trigger
  25. Energy Efficient Approximate Computing Framework for DNN Acceleration Using a Probabilistic-Oriented Method
  26. High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms
  27. SS-MRAM: A Segment-Based Search Scheme With Configurable Matching for High-Accuracy Hyperdimensional Computing in CAM Applications
  28. Dynamic Challenge Cross-Selection Physical Unclonable Function Based on MRAM
  29. E2CAP: An Energy-Efficient FPGA Accelerator for Deep Reinforcement Learning With Experience Compression and Configurable PE Array
  30. ACIMC: A 342.7-TOPS/mm 2 eDRAM-Based Analog Cryogenic In-Memory Computing Macro
  31. A Highly Hardware Efficient ML-KEM Accelerator with Optimised Architectural Layers
  32. A Reinforcement Learning-Based ELF Adversarial Malicious Sample Generation Method
  33. AttnACQ: Attentioned-AutoCorrelation-Based Query for Hyperdimensional Associative Memory
  34. Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication
  35. Memristor-Based Approximate Query Architecture for In-Memory Hyperdimensional Computing
  36. A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices
  37. Guest Editorial: Special Section on “Approximate Data Processing: Computing, Storage and Applications”
  38. An Explainable Intellectual Property Protection Method for Deep Neural Networks Based on Intrinsic Features
  39. SSAT: Active Authorization Control and User’s Fingerprint Tracking Framework for DNN IP Protection
  40. Progressive Approximation-Aware Training with Regularization and Transfer Learning for DNN Acceleration
  41. An Imperceptible and Owner-unique Watermarking Method for Graph Neural Networks
  42. Tracking the Leaker: An Encodable Watermarking Method for Dataset Intellectual Property Protection
  43. A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM
  44. FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations
  45. Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application
  46. Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization
  47. Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme
  48. Untargeted Backdoor Attack Against Deep Neural Networks With Imperceptible Trigger
  49. Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications
  50. VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits
  51. VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
  52. An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
  53. HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining
  54. An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA
  55. Design of High Hardware Efficiency Approximate Floating-Point FFT Processor
  56. High-Throughput Polynomial Multiplier for Accelerating Saber on FPGA
  57. AdvParams: An Active DNN Intellectual Property Protection Technique via Adversarial Perturbation Based Parameter Encryption
  58. Detecting backdoor in deep neural networks via intentional adversarial perturbations
  59. Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS
  60. MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM
  61. ActiveGuard: An active intellectual property protection technique for deep neural networks by leveraging adversarial examples as users' fingerprints
  62. ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations
  63. An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs
  64. Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing
  65. Security and Approximation: Vulnerabilities in Approximation-Aware Testing
  66. Use the Spear as a Shield: An Adversarial Example Based Privacy-Preserving Technique Against Membership Inference Attacks
  67. Approximate Softmax Functions for Energy-Efficient Deep Neural Networks
  68. A 3.8-μW 10-Keyword Noise-Robust Keyword Spotting Processor Using Symmetric Compressed Ternary-Weight Neural Networks
  69. A Survey of Majority Logic Designs in Emerging Nanotechnologies for Computing
  70. High-Performance STT-MRAM-Based Computing-in-Memory Scheme Utilizing Data Read Feature
  71. Low-cost stochastic number generator based on MRAM for stochastic computing
  72. HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation
  73. High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features
  74. Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme
  75. Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits
  76. Intellectual Property Protection for Deep Learning Models: Taxonomy, Methods, Attacks, and Evaluations
  77. Deep Learning-Based Hardware Trojan Detection With Block-Based Netlist Information Extraction
  78. Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs
  79. A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs
  80. A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product
  81. GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy
  82. AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications
  83. Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms
  84. An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits
  85. Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy
  86. A High-Performance SIKE Hardware Accelerator
  87. One-to-N & N-to-One: Two Advanced Backdoor Attacks Against Deep Learning Models
  88. More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network
  89. Design and analysis of energy‐efficient approximate Booth‐folding squarers with precision recovery
  90. Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers
  91. Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers
  92. A Fully Configurable PUF Using Dynamic Variations of Resistive Crossbar Arrays
  93. Design of Majority Logic-Based Approximate Booth Multipliers for Error-Tolerant Applications
  94. Exact and Approximate Squarers for Error-Tolerant Applications
  95. Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation
  96. Design and analysis of hardware Trojans in approximate circuits
  97. An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering
  98. A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation
  99. Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning
  100. Reduced Precision Redundancy for Reliable Processing of Data
  101. Stochastic Dividers for Low Latency Neural Networks
  102. A Real-Time Hardware Emulator for 3D Non-Stationary U2V Channels
  103. An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity
  104. Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers
  105. DNN Intellectual Property Protection
  106. A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication
  107. BCD Adder Designs Based on Three-Input XOR and Majority Gates
  108. Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows
  109. AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators
  110. A Hardware/Software Co-Design Methodology for Adaptive Approximate Computing in clustering and ANN Learning
  111. A Physical Unclonable Function Using a Configurable Tristate Hybrid Scheme With Non-Volatile Memory
  112. APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations
  113. Approximate Computing: From Circuits to Applications
  114. Hybrid Low Radix Encoding-Based Approximate Booth Multipliers
  115. Mathematical Modeling Analysis of Strong Physical Unclonable Functions
  116. Design, evaluation and application of approximate-truncated Booth multipliers
  117. High Performance Modular Multiplication for SIDH
  118. Security Analysis of Hardware Trojans on Approximate Circuits
  119. AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication
  120. Dither-based calibration of bit weights in pipelined-SAR ADCs with fast convergence speed using partially split structure
  121. Embedding Backdoors as the Facial Features
  122. Lightweight Modeling Attack-Resistant Multiplexer-Based Multi-PUF (MMPUF) Design on FPGA
  123. An Efficient and Parallel R-LWE Cryptoprocessor
  124. Guest Editorial: Introduction to the Special Section on Cyber Security Threats and Defense Advance
  125. A Retrospective and Prospective View of Approximate Computing [Point of View}
  126. Attenuation-factor error shaping technique for split CDAC in SAR ADCs
  127. DPAEG: A Dependency Parse-Based Adversarial Examples Generation Method for Intelligent Q&A Robots
  128. Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators
  129. Machine Learning Security: Threats, Countermeasures, and Evaluations
  130. Profile-Based Output Error Compensation for Approximate Arithmetic Circuits
  131. Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3
  132. High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization
  133. Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities
  134. Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits
  135. Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman
  136. New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata
  137. Design and Analysis of Approximate Redundant Binary Multipliers
  138. XOR-Based Low-Cost Reconfigurable PUFs for IoT Security
  139. Building an Accurate Hardware Trojan Detection Technique from Inaccurate Simulation Models and Unlabeled ICs
  140. A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations
  141. Defeating Untrustworthy Testing Parties: A Novel Hybrid Clustering Ensemble Based Golden Models-Free Hardware Trojan Detection Method
  142. Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA
  143. Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition
  144. Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications
  145. Design, Evaluation and Application of Approximate High-Radix Dividers
  146. Design of Dynamic Range Approximate Logarithmic Multipliers
  147. Data Compression Device Based on Modified LZ4 Algorithm
  148. Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design
  149. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
  150. Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications
  151. Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
  152. Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)
  153. Design of Approximate Logarithmic Multipliers
  154. Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition
  155. Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders
  156. Design and Analysis of Inexact Floating-Point Adders
  157. Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing