All Stories

  1. Optimized NTT Architecture Based on the Plantard Algorithm for ML-KEM and ML-DSA
  2. LightHD: A Lightweight and High-Performance Hardware Accelerator of CRYSTALS-Dilithium
  3. Instant-CIM: An Instant Neural Radiance Field Computing-In-Memory Architecture for Low-Power and Real-Time AR/VR Rendering
  4. FPGA-Based Low-Power Signed Approximate Multipliers for Diverse Error-Resilient Applications
  5. A High-Accuracy MRAM-Based Computing-in-Memory Macro for Secure Edge AI Inference
  6. A Lightweight Design of True Random Number Generator Based on Superparamagnetic Tunnel Junction
  7. High-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT
  8. A Highly Reliable Dual-Mode RRAM PUF With Key Concealment Scheme
  9. A 0.071pJ/Bit Flexible Multi-Mode Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF
  10. A Dual-Swing-Sample-and-Couple Sense Amplifier With Large Sensing Margin for STT-MRAM
  11. A Novel Error Metric for Evaluating the Error Correction Capability of Approximate Units
  12. Two Low-Cost and Security-Enhanced Implementations Against Side-Channel Attacks of NTT for Lattice-Based Cryptography
  13. HDANNS: In-Memory Hyperdimensional Computing for Billion-Scale Approximate Nearest Neighbour Search Acceleration
  14. MRAM-Based Cache and In-Memory Computing
  15. An Efficient Methodology for Binary Logarithmic Computations of Floating-Point Numbers With Normalized Output Within One ulp of Accuracy
  16. Temperature-Adaptive TRNG-Encrypted MRAM PUF: Enhancing Resistance to Machine Learning Attacks
  17. Instruction-Based High-Performance Hardware Controller of CRYSTALS-Kyber With Balanced Resource Utilization
  18. Low-Cost Yet Effective Trojan Mitigation Techniques for Approximate Systems
  19. High-Radix Generalized Hyperbolic CORDIC and Its Hardware Implementation
  20. A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications
  21. A High-Speed and High-Yield Path-Switching Sensing Circuit for STT-MRAM
  22. Comparison of Single-Event Transient Under Heavy Ion and Pulsed Laser Irradiation in SiGe HBT Ultrawideband LNA
  23. LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator
  24. 3D Invisible Cloak: A Robust Person Stealth Attack Against Object Detector in Complex 3D Physical Scenarios
  25. A Low-Power and Reliable RRAM-Based Configurable RO PUF With Aging Resilience
  26. A Multi-Mode Configurable Physical Unclonable Function Based on RRAM With Adjustable Programmable Voltage
  27. An Active Authorization Control Method for Deep Reinforcement Learning Model Based on GANs and Adaptive Trigger
  28. Energy Efficient Approximate Computing Framework for DNN Acceleration Using a Probabilistic-Oriented Method
  29. High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms
  30. SS-MRAM: A Segment-Based Search Scheme With Configurable Matching for High-Accuracy Hyperdimensional Computing in CAM Applications
  31. Dynamic Challenge Cross-Selection Physical Unclonable Function Based on MRAM
  32. E2CAP: An Energy-Efficient FPGA Accelerator for Deep Reinforcement Learning With Experience Compression and Configurable PE Array
  33. ACIMC: A 342.7-TOPS/mm 2 eDRAM-Based Analog Cryogenic In-Memory Computing Macro
  34. A Highly Hardware Efficient ML-KEM Accelerator with Optimised Architectural Layers
  35. A Reinforcement Learning-Based ELF Adversarial Malicious Sample Generation Method
  36. AttnACQ: Attentioned-AutoCorrelation-Based Query for Hyperdimensional Associative Memory
  37. Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication
  38. Memristor-Based Approximate Query Architecture for In-Memory Hyperdimensional Computing
  39. A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices
  40. Guest Editorial: Special Section on “Approximate Data Processing: Computing, Storage and Applications”
  41. An Explainable Intellectual Property Protection Method for Deep Neural Networks Based on Intrinsic Features
  42. SSAT: Active Authorization Control and User’s Fingerprint Tracking Framework for DNN IP Protection
  43. Progressive Approximation-Aware Training with Regularization and Transfer Learning for DNN Acceleration
  44. An Imperceptible and Owner-unique Watermarking Method for Graph Neural Networks
  45. Tracking the Leaker: An Encodable Watermarking Method for Dataset Intellectual Property Protection
  46. A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM
  47. FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations
  48. Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application
  49. Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization
  50. Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme
  51. Untargeted Backdoor Attack Against Deep Neural Networks With Imperceptible Trigger
  52. Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications
  53. VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits
  54. VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
  55. An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
  56. HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining
  57. An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA
  58. Design of High Hardware Efficiency Approximate Floating-Point FFT Processor
  59. High-Throughput Polynomial Multiplier for Accelerating Saber on FPGA
  60. AdvParams: An Active DNN Intellectual Property Protection Technique via Adversarial Perturbation Based Parameter Encryption
  61. Detecting backdoor in deep neural networks via intentional adversarial perturbations
  62. Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS
  63. MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM
  64. ActiveGuard: An active intellectual property protection technique for deep neural networks by leveraging adversarial examples as users' fingerprints
  65. ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations
  66. An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs
  67. Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing
  68. Security and Approximation: Vulnerabilities in Approximation-Aware Testing
  69. Use the Spear as a Shield: An Adversarial Example Based Privacy-Preserving Technique Against Membership Inference Attacks
  70. Approximate Softmax Functions for Energy-Efficient Deep Neural Networks
  71. A 3.8-μW 10-Keyword Noise-Robust Keyword Spotting Processor Using Symmetric Compressed Ternary-Weight Neural Networks
  72. A Survey of Majority Logic Designs in Emerging Nanotechnologies for Computing
  73. High-Performance STT-MRAM-Based Computing-in-Memory Scheme Utilizing Data Read Feature
  74. Low-cost stochastic number generator based on MRAM for stochastic computing
  75. HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation
  76. High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features
  77. Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme
  78. Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits
  79. Intellectual Property Protection for Deep Learning Models: Taxonomy, Methods, Attacks, and Evaluations
  80. Deep Learning-Based Hardware Trojan Detection With Block-Based Netlist Information Extraction
  81. Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs
  82. A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs
  83. A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product
  84. GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy
  85. AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications
  86. Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms
  87. An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits
  88. Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy
  89. A High-Performance SIKE Hardware Accelerator
  90. One-to-N & N-to-One: Two Advanced Backdoor Attacks Against Deep Learning Models
  91. More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network
  92. Design and analysis of energy‐efficient approximate Booth‐folding squarers with precision recovery
  93. Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers
  94. Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers
  95. A Fully Configurable PUF Using Dynamic Variations of Resistive Crossbar Arrays
  96. Design of Majority Logic-Based Approximate Booth Multipliers for Error-Tolerant Applications
  97. Exact and Approximate Squarers for Error-Tolerant Applications
  98. Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation
  99. Design and analysis of hardware Trojans in approximate circuits
  100. An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering
  101. A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation
  102. Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning
  103. Reduced Precision Redundancy for Reliable Processing of Data
  104. Stochastic Dividers for Low Latency Neural Networks
  105. A Real-Time Hardware Emulator for 3D Non-Stationary U2V Channels
  106. An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity
  107. Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers
  108. DNN Intellectual Property Protection
  109. A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication
  110. BCD Adder Designs Based on Three-Input XOR and Majority Gates
  111. Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows
  112. AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators
  113. Stochastic Dividers for Low Latency Neural Networks
  114. A Hardware/Software Co-Design Methodology for Adaptive Approximate Computing in clustering and ANN Learning
  115. A Physical Unclonable Function Using a Configurable Tristate Hybrid Scheme With Non-Volatile Memory
  116. APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations
  117. Approximate Computing: From Circuits to Applications
  118. Hybrid Low Radix Encoding-Based Approximate Booth Multipliers
  119. Mathematical Modeling Analysis of Strong Physical Unclonable Functions
  120. Design, evaluation and application of approximate-truncated Booth multipliers
  121. High Performance Modular Multiplication for SIDH
  122. Security Analysis of Hardware Trojans on Approximate Circuits
  123. AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication
  124. Dither-based calibration of bit weights in pipelined-SAR ADCs with fast convergence speed using partially split structure
  125. Embedding Backdoors as the Facial Features
  126. Lightweight Modeling Attack-Resistant Multiplexer-Based Multi-PUF (MMPUF) Design on FPGA
  127. An Efficient and Parallel R-LWE Cryptoprocessor
  128. Guest Editorial: Introduction to the Special Section on Cyber Security Threats and Defense Advance
  129. A Retrospective and Prospective View of Approximate Computing [Point of View}
  130. Attenuation-factor error shaping technique for split CDAC in SAR ADCs
  131. DPAEG: A Dependency Parse-Based Adversarial Examples Generation Method for Intelligent Q&A Robots
  132. Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators
  133. Machine Learning Security: Threats, Countermeasures, and Evaluations
  134. Profile-Based Output Error Compensation for Approximate Arithmetic Circuits
  135. Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3
  136. High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization
  137. Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities
  138. Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits
  139. Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman
  140. New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata
  141. Design and Analysis of Approximate Redundant Binary Multipliers
  142. XOR-Based Low-Cost Reconfigurable PUFs for IoT Security
  143. Building an Accurate Hardware Trojan Detection Technique from Inaccurate Simulation Models and Unlabeled ICs
  144. A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations
  145. Defeating Untrustworthy Testing Parties: A Novel Hybrid Clustering Ensemble Based Golden Models-Free Hardware Trojan Detection Method
  146. Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA
  147. Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition
  148. Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications
  149. Design, Evaluation and Application of Approximate High-Radix Dividers
  150. Design of Dynamic Range Approximate Logarithmic Multipliers
  151. Data Compression Device Based on Modified LZ4 Algorithm
  152. Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design
  153. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
  154. Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications
  155. Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
  156. Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)
  157. Design of Approximate Logarithmic Multipliers
  158. Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition
  159. Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders
  160. Design and Analysis of Inexact Floating-Point Adders
  161. Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing