All Stories

  1. Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms

    Article • IEEE Computer Architecture Letters, January 2024, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  2. OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators

    Article • ACM Transactions on Embedded Computing Systems, November 2022, ACM (Association for Computing Machinery)

    Dr. Subhankar Pal

  3. Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory

    Article • IEEE Journal of Solid-State Circuits, April 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  4. A Holistic Solution for Reliability of 3D Parallel Systems

    Article • ACM Journal on Emerging Technologies in Computing Systems, January 2022, ACM (Association for Computing Machinery)

    Dr. Subhankar Pal

  5. CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics

    Article • December 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  6. SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator

    Article • October 2021, ACM (Association for Computing Machinery)

    Dr. Subhankar Pal

  7. Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles

    Article • IEEE Computer Architecture Letters, July 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  8. Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm

    Article • June 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  9. Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators

    Article • March 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  10. HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework

    Article • October 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  11. Transmuter

    Article • September 2020, ACM (Association for Computing Machinery)

    Chi-Sheng Yang, Dr. Subhankar Pal

  12. R2D3: A Reliability Engine for 3D Parallel Systems

    Article • July 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  13. Sparse-TPU

    Article • June 2020, ACM (Association for Computing Machinery)

    Dr. Subhankar Pal

  14. Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture

    Article • May 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  15. A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator

    Article • IEEE Journal of Solid-State Circuits, April 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  16. A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm

    Article • June 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  17. A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm

    Article • June 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  18. Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective

    Article • March 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  19. OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator

    Article • February 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  20. A carbon nanotube transistor based RISC-V processor using pass transistor logic

    Article • July 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal

  21. A New Design of an N-Bit Reversible Arithmetic Logic Unit

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Subhankar Pal