All Stories

  1. Energy-Aware Fault-Tolerant Mapping of Mixed-Criticality Tasks on Heterogeneous Multicores
  2. Synapse: Synergizing Approximate STT-MRAM and CNN Features for Energy-Efficient Accelerators
  3. Padel: Priority-Based Real-Time Scheduling for GPUs
  4. ReTMiC: Reliability-Aware Thermal Management in Multicore Mixed-Criticality Embedded Systems
  5. Cluster-based cooperative fog caching for scalable coded videos of multiple content providers
  6. A Robust Heterogeneous Offloading Setup Using Adversarial Training
  7. LEC-MiCs: Low-Energy Checkpointing in Mixed-Criticality Multi-Core Systems
  8. Cross-Core Data Sharing for Energy-Efficient GPUs
  9. Tulip: Turn-Free Low-Power Network-on-Chip
  10. On the Effectiveness of Fog Offloading in a Mobility-Aware Healthcare Environment
  11. TherMa-MiCs: Thermal-Aware Scheduling for Fault-Tolerant Mixed-Criticality Systems
  12. HFOS$$_L$$: hyper scale fast optical switch-based data center network with L-level sub-network
  13. A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues
  14. Power-Aware Checkpointing for Multicore Embedded Systems
  15. Power-gating in NoCs
  16. Enhancing Reliability of Emerging Memory Technology for Machine Learning Accelerators
  17. REALISM: Reliability-aware energy management in multi-level mixed-criticality systems with service level degradation
  18. Tolerating Permanent Faults with Low-Energy Overhead in Multicore Mixed-Criticality Systems
  19. LESS-MICS: A Low Energy Standby-Sparing Scheme for Mixed-Criticality Systems
  20. Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators
  21. Aging-Aware Context Switching in Multicore Processors Based on Workload Classification
  22. A Simple and Fast Solution for Fault Simulation Using Approximate Parallel Critical Path Tracing
  23. On the Scheduling of Energy-Aware Fault-Tolerant Mixed-Criticality Multicore Systems with Service Guarantee Exploration
  24. Toward On-chip Network Security Using Runtime Isolation Mapping
  25. A thermally-resilient all-optical network-on-chip
  26. Low-overhead thermally resilient optical network-on-chip architecture
  27. A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology
  28. A low-power single-ended SRAM in FinFET technology
  29. SPONGE
  30. PyCM: Multiclass confusion matrix library in Python
  31. Behavioral-level hardware trust: Analysis and enhancement
  32. DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture
  33. A robust and low-power near-threshold SRAM in 10-nm FinFET technology
  34. Topology exploration of a thermally resilient wavelength-based ONoC
  35. A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard
  36. Thermal and power aware task mapping on 3D Network on Chip
  37. Low Energy yet Reliable Data Communication Scheme for Network-on-Chip
  38. Application-based dynamic reconfiguration in optical network-on-chip
  39. Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design
  40. Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality
  41. Power-efficient prefetching on GPGPUs
  42. Towards a scalable, low-power all-optical architecture for networks-on-chip
  43. All-Optical Wavelength-Routed Architecture for a Power-Efficient Network on Chip
  44. An Efficient Synchronization Circuit in Multi-Rate SDH Networks
  45. Temperature control in three‐network on chips using task migration
  46. Scalable architecture for a contention-free optical network on-chip
  47. Power-efficient deterministic and adaptive routing in torus networks-on-chip
  48. Throughput enhancement for repetitive internal cores in latency-insensitive systems
  49. GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses
  50. Hierarchical opto-electrical on-chip network for future multiprocessor architectures
  51. Advances in Computer Science and Engineering
  52. A FRAMEWORK FOR OBJECT-ORIENTED EMBEDDED SYSTEM DEVELOPMENT BASED ON OO-ASIPS
  53. Timing verification of distributed network systems at higher levels of abstraction
  54. The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model
  55. PERMAP: A performance-aware mapping for application-specific SoCs
  56. A Novel Partitioned Encoding Scheme for Reducing Total Power Consumption of Parallel Bus
  57. An Adaptive Approach to Manage the Number of Virtual Channels
  58. Caspian: A Tunable Performance Model for Multi-core Systems
  59. Integration of System-Level IP Cores in Object-Oriented Design Methodologies
  60. Polymorphism-Aware Common Bus in an Object-Oriented ASIP
  61. System-Level Assertion-Based Performance Verification for Embedded Systems
  62. Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems
  63. An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits
  64. Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs
  65. An assertion-based verification methodology for system-level design
  66. DotGrid: a .NET-based cross-platform software for desktop grids
  67. A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems
  68. On the Hardware-Software Partitioning: The Classic General Model (CGM)
  69. DESIGN OF VARIABLE FRACTIONAL DELAY FIR FILTERS WITH CSD COEFFICIENTS USING GENETIC ALGORITHM
  70. AN ACCURATE FIR APPROXIMATION OF IDEAL FRACTIONAL DELAY FILTER WITH COMPLEX COEFFICIENTS IN HILBERT SPACE
  71. A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems
  72. Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance
  73. The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models
  74. Differential BiCMOS logic circuits: fault characterization and design-for-testability
  75. High-level symbolic simulation using integer equations
  76. Rapid design space exploration of DSP applications using programmable SoC devices-a case study