All Stories

  1. Invited: Toward Accurate, Large-scale Electromigration Analysis and Optimization in Integrated Systems
  2. An Analytical Solution for Transient Electromigration Stress in Multisegment Straight-line Interconnects Based on a Stress-wave Model
  3. Invited: Toward an ML EDA Commons: Establishing Standards, Accessibility, and Reproducibility in ML-driven EDA Research
  4. Towards Designing and Deploying Ising Machines
  5. Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators
  6. Analyzing the Impact of FinFET Self-Heating on the Performance of RF Power Amplifiers
  7. Generative Methods in EDA: Innovations in Dataset Generation and EDA Tool Assistants
  8. IR-Aware ECO Timing Optimization Using Reinforcement Learning
  9. Hardware Acceleration of Inference on Dynamic GNNs
  10. On Error Correction for Nonvolatile Processing-In-Memory
  11. An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators
  12. A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route
  13. On Endurance of Processing in (Nonvolatile) Memory
  14. The ALIGN Automated Analog Layout Engine
  15. Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects
  16. A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/Mixed-Signal Layouts
  17. Performance-driven Wire Sizing for Analog Integrated Circuits
  18. Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks
  19. A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment Interconnects
  20. Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions
  21. Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms
  22. From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction
  23. Analog/Mixed-Signal Layout Optimization using Optimal Well Taps
  24. Spiking Neural Networks in Spintronic Computational RAM
  25. CAMeleon
  26. Machine Learning Techniques in Analog Layout Automation
  27. A customized graph neural network model for guiding analog IC placement
  28. PIMBALL
  29. Stress-Induced Performance Shifts in 3D DRAMs
  30. ALIGN
  31. True In-memory Computing with the CRAM
  32. Strain-aware performance evaluation and correction for OTFT-based flexible displays
  33. Control synthesis and delay sensor deployment for efficient ASV designs
  34. Optimal design of JPEG hardware under the approximate computing paradigm
  35. Joint precision optimization and high level synthesis for approximate computing