All Stories

  1. A Theoretical Foundation for Timing Synchronous Systems Using Asynchronous Structures

    Article • ACM Transactions on Design Automation of Electronic Systems, March 2020, ACM (Association for Computing Machinery)

    Ramy N Tadros

  2. How to design delay elements for some classes of asynchronous circuits

    Article • ACM Journal on Emerging Technologies in Computing Systems, March 2017, ACM (Association for Computing Machinery)

    Ramy N Tadros, Ney Calazans

  3. Ultra-Low Power PTL-based Delay Line Design for Sub-threshold Applications

    Article • Electronics Letters, October 2016, the Institution of Engineering and Technology (the IET)

    Ramy N Tadros

  4. A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, September 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Ramy N Tadros

  5. Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures

    Article • August 2016, ACM (Association for Computing Machinery)

    Ramy N Tadros

  6. Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications

    Article • May 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Ramy N Tadros

  7. 2 ps resolution, fine-grained delay element in 28 nm FDSOI

    Article • Electronics Letters, November 2015, the Institution of Engineering and Technology (the IET)

    Ramy N Tadros

  8. A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies

    Article • July 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Ramy N Tadros

  9. A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme

    Article • March 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Ramy N Tadros

  10. Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks

    Article • June 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Ramy N Tadros

  11. A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks

    Article • June 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Ramy N Tadros