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  1. Fast paraphrase extraction in Ancient Greek literature

    Article • it - Information Technology, April 2020, De Gruyter

    Prof. Dr. Paul Molitor, Janis Dähne

  2. Digital methods for intertextuality studies

    Article • it - Information Technology, April 2020, De Gruyter

    Prof. Dr. Paul Molitor

  3. Computational Recognition of RNA Splice Sites by Exact Algorithms for the Quadratic Traveling Salesman Problem

    Article • Computation, June 2015, MDPI AG

    Professor Ivo Grosse, Prof. Dr. Paul Molitor

  4. „im Zentrum eines Netzes [...] geistiger Fäden“. Erschließung und Erforschung thematischer Zusammenhänge in heterogenen Briefkorpora

    Article • Datenbank-Spektrum, February 2015, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  5. Zum Einsatz digitaler Methoden bei der Erstellung und Nutzung genetischer Editionen gedruckter Texte mit verschiedenen Fassungen

    Article • editio - International Yearbooks for Scholarly Editing / Internationales Jahrbuch für Editionswissenschaft, January 2015, De Gruyter

    Prof. Dr. Paul Molitor

  6. Differenzanalyse komplexer Textvarianten

    Article • Datenbank-Spektrum, January 2015, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  7. An optimized platform for capturing metadata of historical correspondence

    Article • Digital Scholarship in the Humanities, June 2014, Oxford University Press (OUP)

    Prof. Dr. Paul Molitor

  8. Exact algorithms and heuristics for the Quadratic Traveling Salesman Problem with an application in bioinformatics

    Article • Discrete Applied Mathematics, March 2014, Elsevier

    Prof. Dr. Paul Molitor

  9. A backbone based TSP heuristic for large instances

    Article • Journal of Heuristics, December 2013, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  10. Kompaktkurs VDHL

    Article • January 2013, De Gruyter

    Prof. Dr. Paul Molitor

  11. Finding Good Tours for Huge Euclidean TSP Instances by Iterative Backbone Contraction

    Article • January 2010, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  12. Guiding property development with SAT-based coverage calculation

    Article • August 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  13. Effective Tour Searching for TSP by Contraction of Pseudo Backbone Edges

    Article • January 2009, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  14. Client Hardware-Token Based Single Sign-On over Several Servers without Trusted Online Third Party Server

    Article • January 2009, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  15. Technische Informatik

    Article • January 2008, De Gruyter

    Prof. Dr. Paul Molitor

  16. What Graphs can be Efficiently Represented by BDDs?

    Article • March 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  17. Tolerances Applied in Combinatorial Optimization

    Article • Journal of Computer Science, September 2006, Science Publications

    Prof. Dr. Paul Molitor

  18. … was wird mit übrigens?

    Article • it - Information Technology, January 2006, De Gruyter

    Prof. Dr. Paul Molitor

  19. Some Basics on Tolerances

    Article • January 2006, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  20. Tolerance Based Contract-or-Patch Heuristic for the Asymmetric TSP

    Article • January 2006, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  21. Article • Formal Methods in System Design, January 2003, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  22. Article • Formal Methods in System Design, January 2002, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  23. k-Layer Straightline Crossing Minimization by Speeding Up Sifting

    Article • January 2001, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  24. A pipelined architecture for partitioned DWT based lossy image compression using FPGA's

    Article • January 2001, ACM (Association for Computing Machinery)

    Prof. Dr. Paul Molitor

  25. Least upper bounds for the size of OBDDs using symmetry properties

    Article • IEEE Transactions on Computers, April 2000, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  26. An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines

    Article • January 2000, ACM (Association for Computing Machinery)

    Prof. Dr. Paul Molitor

  27. Prove that a faulty multiplier is faulty!?

    Article • January 2000, ACM (Association for Computing Machinery)

    Prof. Dr. Paul Molitor

  28. Using Sifting for k-Layer Straightline Crossing Minimization

    Article • January 1999, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  29. Establishing latch correspondence for sequential circuits using distinguishing signatures

    Article • Integration, January 1999, Elsevier

    Prof. Dr. Paul Molitor

  30. BDD minimization using symmetries

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 1999, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  31. New crossover methods for sequencing problems

    Article • January 1996, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  32. Symmetry Based Variable Ordering for ROBDDs

    Article • January 1995, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  33. Efficient ROBDD based computation of common decomposition functions of multi-output boolean functions

    Article • January 1995, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  34. Limits of using signatures for permutation independent Boolean comparison

    Article • January 1995, ACM (Association for Computing Machinery)

    Prof. Dr. Paul Molitor

  35. Communication based FPGA synthesis for multi-output Boolean functions

    Article • January 1995, ACM (Association for Computing Machinery)

    Prof. Dr. Paul Molitor

  36. On the generation of area-time optimal testable adders

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 1995, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  37. A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization

    Article • Integration, July 1993, Elsevier

    Prof. Dr. Paul Molitor

  38. Performance driven k-layer wiring

    Article • January 1992, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  39. A Hierarchy Preserving Hierarchical Bottom-Up 2-layer Wiring Algorithm with Respect to Via Minimization

    Article • January 1992, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  40. Minimal stretching of a layout to ensure 2-layer wirability

    Article • Integration, December 1991, Elsevier

    Prof. Dr. Paul Molitor

  41. Euro ASIC '91 (Cat. No.91TH0367-3)

    Article • January 1991, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  42. Constrained via minimization for systolic arrays

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 1990, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  43. A note on hierarchical layer-assignment

    Article • Integration, September 1989, Elsevier

    Prof. Dr. Paul Molitor

  44. Einführung in den VLSI-Entwurf

    Article • January 1989, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  45. On network algebras and recursive equations

    Article • January 1987, Springer Science + Business Media

    Prof. Dr. Paul Molitor

  46. Hierarchical design based on a calculus of nets

    Article • January 1987, ACM (Association for Computing Machinery)

    Prof. Dr. Paul Molitor

  47. Layer assignment by simulated annealing

    Article • Microprocessing and Microprogramming, November 1985, Elsevier

    Prof. Dr. Paul Molitor

  48. On the contact-minimization-problem

    Article • Springer Science + Business Media

    Prof. Dr. Paul Molitor

  49. Priority driven channel pin assignment

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  50. Algorithms and Experimental Study for the Traveling Salesman Problem of Second Order

    Article • Springer Science + Business Media

    Prof. Dr. Paul Molitor

  51. Improving the Efficiency of Helsgaun’s Lin-Kernighan Heuristic for the Symmetric TSP

    Article • Springer Science + Business Media

    Prof. Dr. Paul Molitor

  52. SPIHT implemented in a XC4000 device

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  53. A partitioned wavelet-based approach for image compression using FPGA's

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  54. An efficient heuristic for state encoding minimizing the BDD representations of the transition relations of finite state machines

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  55. Simulating field programmable analog devices

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  56. Minimizing ROBDD sizes of incompletely specified Boolean functions by exploiting strong symmetries

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  57. Vertical floating pins in OTC routing [VLSI layout]

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  58. Least upper bounds on the sizes of symmetric variable order based OBDDs

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  59. Communication based FPGA synthesis for multi-output Boolean functions

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  60. Limits of using signatures for permutation independent Boolean comparison

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor

  61. Two-layer wiring with pin preassignments is easier if the power supply nets are already generated

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Dr. Paul Molitor