All Stories

  1. An optimized design of reversible magnitude and signed comparators

    Article • August 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao

  2. Reversible Radix-4 booth multiplier for DSP applications

    Article • June 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao

  3. An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits

    Article • Journal of Electronic Testing, March 2016, Springer Science + Business Media

    Mrs Nagamani A N Rao

  4. Design of register file using reversible logic

    Article • March 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao

  5. Design and Analysis of Reversible Binary and BCD Adders

    Article • December 2015, Springer Science + Business Media

    Mrs Nagamani A N Rao

  6. Design of optimized reversible multiplier for high speed DSP application

    Article • December 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao

  7. Deterministic approach for bridging fault detection in Peres-Fredkin and Toffoli based reversible circuits

    Article • December 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao

  8. Design of priority encoding based reversible comparators

    Article • June 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao

  9. Design of optimized reversible Binary and BCD adders

    Article • January 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao

  10. Design of Quantum Cost and Delay-Optimized Reversible Wallace Tree Multiplier Using Compressors

    Article • November 2014, Springer Science + Business Media

    Mrs Nagamani A N Rao

  11. Design of optimized reversible binary adder/subtractor and BCD adder

    Article • November 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao

  12. On the design of hazard free reversible asynchronous circuits

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao

  13. Design and analysis of ESOP based online testable reversible SRAM array

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao

  14. Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder

    Article • January 2013, Springer Science + Business Media

    Mrs Nagamani A N Rao

  15. Quaternary High Performance Arithmetic Logic Unit Design

    Article • August 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Mrs Nagamani A N Rao