All Stories

  1. A New Phasorial Oriented Single PI Loop Control for Industrial VSC-PFC Rectifiers Operating Under Unbalanced Conditions
  2. THD Reduction in Distributed Renewables Energy Access through Wind Energy Conversion System Integration under Wind Speed Conditions in Tamaulipas, Mexico
  3. Reactive Power Compensation in Distribution Systems Through the DSTATCOM Integration Based on the Bond Graph Domain
  4. THD Reduction in Wind Energy System Using Type-4 Wind Turbine/PMSG Applying the Active Front-End Converter Parallel Operation
  5. THD Reduction in Wind Energy System Using Type-4 Wind Turbine/PMSG Applying the Active Front-End Converter Parallel Operation
  6. Active Front-End converter applied for the THD reduction in power systems
  7. Current-Sensorless VSC-PFC Rectifier Control With Enhance Response to Dynamic and Sag Conditions Using a Single PI Loop
  8. Reactive Power Compensation in Wind Energy Systems through Resonant Corrector in Distributed Static Compensator
  9. DSPWM multilevel technique of 27-levels based on FPGA for the cascaded DC/AC power converter operation
  10. PI tuning parameters in back-to-back converters applying active damping control for DC-voltage power port regulation
  11. Sags and swells compensation and power factor correction using a dynamic voltage restorer in distribution systems
  12. Reactive power compensation in distributed networks with wind turbine integration using resonant corrector
  13. Reactive power compensation through active back to back converter in type-4 wind turbine
  14. Reactive power regulation and voltage compensation through DSTATCOM with wind turbine integration
  15. THD mitigation in type-4 Wind Turbine through AFE Back to back converter
  16. Step-up Transformerless Seven-level DC-AC Hybrid Topology for Interconnection of Renewable-based DC Sources to Microgrids
  17. Transformerless, 9-levels DC/AC hybrid topology based on single DC source, for renewable power applications
  18. Generation of a multilevel SPWM technique of 3, 9 and 21 levels with FPGAs