All Stories

  1. LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference

    Article • January 2025, ACM (Association for Computing Machinery)

    Miriam Leeser

  2. Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function

    Article • April 2024, ACM (Association for Computing Machinery)

    Miriam Leeser

  3. Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track

    Article • ACM Transactions on Reconfigurable Technology and Systems, June 2023, ACM (Association for Computing Machinery)

    Miriam Leeser

  4. FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization

    Article • July 2022, ACM (Association for Computing Machinery)

    Miriam Leeser

  5. Strategies and Demonstration to Support Multiple Wireless Protocols with a Single RF Front-End

    Article • IEEE Wireless Communications, June 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  6. A Novel Physical Layer Authentication With PAPR Reduction Based on Channel and Hardware Frequency Responses

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, February 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser, David Malone

  7. Real Time Receiver Baseband Processing Platform for Sub 6 GHz PHY Layer Experiments

    Article • IEEE Access, January 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  8. SIFO: Secure Computational Infrastructure Using FPGA Overlays

    Article • International Journal of Reconfigurable Computing, December 2019, Hindawi Publishing Corporation

    Xin Fang, Miriam Leeser

  9. QuTiBench

    Article • ACM Journal on Emerging Technologies in Computing Systems, October 2019, ACM (Association for Computing Machinery)

    Miriam Leeser

  10. Garbled Circuits in the Cloud using FPGA Enabled Nodes

    Article • September 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  11. Detection of Different Wireless Protocols on an FPGA with the Same Analog/RF Front End

    Article • January 2019, Springer Science + Business Media

    Miriam Leeser

  12. High-Level and Compact Design of Cross-Channel LTE DownLink Channel Encoder

    Article • January 2019, Springer Science + Business Media

    Miriam Leeser

  13. FINN- R

    Article • ACM Transactions on Reconfigurable Technology and Systems, September 2018, ACM (Association for Computing Machinery)

    Miriam Leeser

  14. Local and Global Shared Memory for Task Based HPC Applications on Heterogeneous Platforms

    Article • March 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  15. Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic

    Article • November 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  16. Accelerating big data applications using lightweight virtualization framework on enterprise cloud

    Article • September 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  17. FPGA modeling techniques for detecting and demodulating multiple wireless protocols

    Article • September 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  18. FIM: Performance Prediction for Parallel Computation in Iterative Data Processing Applications

    Article • June 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  19. Secure Function Evaluation Using an FPGA Overlay Architecture

    Article • February 2017, ACM (Association for Computing Machinery)

    Miriam Leeser

  20. A Framework for Developing Parallel Applications with high level Tasks on Heterogeneous Platforms

    Article • January 2017, ACM (Association for Computing Machinery)

    Miriam Leeser

  21. Using High Level GPU Tasks to Explore Memory and Communications Options on Heterogeneous Platforms

    Article • January 2017, ACM (Association for Computing Machinery)

    Miriam Leeser

  22. Performance prediction techniques for scalable large data processing in distributed MPI systems

    Article • December 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  23. Open-Source Variable-Precision Floating-Point Library for Major Commercial FPGAs

    Article • ACM Transactions on Reconfigurable Technology and Systems, September 2016, ACM (Association for Computing Machinery)

    Miriam Leeser

  24. Design space exploration of GPU Accelerated cluster systems for optimal data transfer using PCIe bus

    Article • September 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  25. Unified and lightweight tasks and conduits: A high level parallel programming framework

    Article • September 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  26. State-Action Based Link Layer Design for IEEE 802.11b Compliant MATLAB-Based SDR

    Article • May 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  27. High-level hardware-software co-design of an 802.11a transceiver system using Zynq SoC

    Article • April 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  28. Cardiac MRI compressed sensing image reconstruction with a graphics processing unit

    Article • March 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  29. High-Level System Design of IEEE 802.11b Standard-Compliant Link Layer for MATLAB-Based SDR

    Article • IEEE Access, January 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  30. Validity and reliability of Kinect skeleton for measuring shoulder joint angles: a feasibility study

    Article • Physiotherapy, December 2015, Elsevier

    Miriam Leeser

  31. Accelerating K-Means clustering with parallel implementations and GPU computing

    Article • September 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  32. GPU implementation of reverse coordinate conversion for proteins

    Article • September 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  33. Leakage evaluation on power balance countermeasure against side-channel attack on FPGAs

    Article • September 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  34. Balance power leakage to fight against side-channel analysis at gate level in FPGAs

    Article • July 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  35. Side-channel analysis of MAC-Keccak hardware implementations

    Article • June 2015, ACM (Association for Computing Machinery)

    Miriam Leeser, David Kaeli

  36. Accuracy of kinect for measuring shoulder joint angles in multiple planes of motion

    Article • June 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  37. Kernel Specialization Provides Adaptable GPU Code for Particle Image Velocimetry

    Article • IEEE Transactions on Parallel and Distributed Systems, April 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  38. Behavioral Non-portability in Scientific Numeric Computing

    Article • January 2015, Springer Science + Business Media

    Miriam Leeser

  39. Implementing a MATLAB-Based Self-configurable Software Defined Radio Transceiver

    Article • January 2015, Springer Science + Business Media

    Miriam Leeser

  40. Power analysis attack on hardware implementation of MAC-Keccak on FPGAs

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  41. Accelerating protein coordinate conversion using GPUs

    Article • September 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  42. Fast reconstruction of 3D volumes from 2D CT projection data with GPUs

    Article • BMC Research Notes, August 2014, Springer Science + Business Media

    Miriam Leeser

  43. Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework

    Article • May 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  44. Validity and reliability of kinect for measuring shoulder joint angles

    Article • April 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  45. Make it real: Effective floating-point reasoning via exact arithmetic

    Article • January 2014, EDAA

    Miriam Leeser

  46. FPGA-based hyperspectral covariance coprocessor for size, weight, and power constrained platforms

    Article • September 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  47. Vendor agnostic, high performance, double precision Floating Point division for FPGAs

    Article • September 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  48. Development of a low-cost, adaptive, clinician-friendly virtual rehabilitation system

    Article • August 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  49. Kernel Specialization for Improved Adaptability and Performance on Graphics Processing Units (GPUs)

    Article • May 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  50. A Message from the General Chair and Program Chair

    Article • April 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  51. Minimum energy operation for clustered island-style FPGAs

    Article • January 2013, ACM (Association for Computing Machinery)

    Miriam Leeser

  52. Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  53. Characterization of a single-supply subthreshold FPGA

    Article • October 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  54. Cognitive radio universal software hardware

    Article • October 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  55. CUDA and OpenCL implementations of 3D CT reconstruction for biomedical imaging

    Article • September 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  56. VForce: An environment for portable applications on high performance systems with accelerators

    Article • Journal of Parallel and Distributed Computing, September 2012, Elsevier

    Miriam Leeser

  57. CRUSH: Cognitive Radio Universal Software Hardware

    Article • August 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  58. Heterogeneous tasks and conduits framework for rapid application portability and deployment

    Article • May 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  59. Cognitive Radio Universal Software Hardware

    Article • April 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  60. Incremental clustering applied to radar deinterleaving

    Article • January 2012, ACM (Association for Computing Machinery)

    Miriam Leeser

  61. Adaptable Two-Dimension Sliding Windows on NVIDIA GPUs with Runtime Compilation

    Article • July 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  62. An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs

    Article • May 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  63. VFloat

    Article • ACM Transactions on Reconfigurable Technology and Systems, September 2010, ACM (Association for Computing Machinery)

    Miriam Leeser

  64. Efficient template matching with variable size templates in CUDA

    Article • June 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  65. A truly two-dimensional systolic array FPGA implementation of QR decomposition

    Article • ACM Transactions on Embedded Computing Systems, October 2009, ACM (Association for Computing Machinery)

    Miriam Leeser

  66. Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware

    Article • July 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  67. Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA

    Article • January 2009, ACM (Association for Computing Machinery)

    Miriam Leeser

  68. FPGA Supercomputing Platforms, Architectures, and Techniques for Accelerating Computationally Complex Algorithms

    Article • EURASIP Journal on Embedded Systems, January 2009, Springer Science + Business Media

    Miriam Leeser

  69. Parallel Backprojection: A Case Study in High-Performance Reconfigurable Computing

    Article • EURASIP Journal on Embedded Systems, January 2009, Springer Science + Business Media

    Miriam Leeser

  70. Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison

    Article • November 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  71. Special issue: General-purpose processing using graphics processing units

    Article • Journal of Parallel and Distributed Computing, October 2008, Elsevier

    Miriam Leeser

  72. Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, August 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  73. An efficient implementation of a phase unwrapping kernel on reconfigurable hardware

    Article • July 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  74. An FPGA Implementation of Explicit-State Model Checking

    Article • April 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  75. An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware

    Article • April 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  76. Dynamo: a runtime partitioning system for FPGA-based HW/SW image processing systems

    Article • Journal of Real-Time Image Processing, November 2007, Springer Science + Business Media

    Miriam Leeser

  77. K-means Clustering for Multispectral Images Using Floating-Point Divide

    Article • April 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  78. Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware

    Article • April 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  79. Vforce: An Extensible Framework for Reconfigurable Supercomputing

    Article • Computer, March 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  80. Advanced Components in the Variable Precision Floating-Point Library

    Article • April 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  81. Automatic Sliding Window Operation Optimization for FPGA-Based

    Article • April 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  82. Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency

    Article • IEEE Transactions on Multimedia, February 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  83. Real-Time Particle Image Velocimetry for Feedback Loops Using FPGA Implementation

    Article • Journal of Aerospace Information Systems, February 2006, American Institute of Aeronautics and Astronautics (AIAA)

    Miriam Leeser

  84. Field-Programmable Gate Arrays in Embedded Systems

    Article • EURASIP Journal on Embedded Systems, January 2006, Springer Science + Business Media

    Miriam Leeser

  85. Poster reception---Improving the performance of parallel backprojection on a reconfigurable supercomputer

    Article • January 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  86. Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging

    Article • The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, March 2005, Springer Science + Business Media

    Miriam Leeser

  87. Optimizing data intensive window-based image processing on reconfigurable hardware boards

    Article • January 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  88. Applying reconfigurable hardware to the analysis of multispectral and hyperspectral imagery

    Article • January 2002, SPIE

    Miriam Leeser

  89. Accurate Power Estimation for Sequential CMOS Circuits Using Graph-based Methods

    Article • VLSI Design, January 2001, Hindawi Publishing Corporation

    Miriam Leeser

  90. Design issues for hardware implementation of an algorithm for segmenting hyperspectral imagery

    Article • November 2000, SPIE

    Miriam Leeser

  91. Effect of data truncation in an implementation of pixel clustering on a custom computing machine

    Article • October 2000, SPIE

    Miriam Leeser

  92. HML, a novel hardware description language and its translation to VHDL

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, February 2000, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  93. A data-centric approach to high-level synthesis

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 2000, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  94. Spatial and color clustering on an FPGA-based computer system

    Article • October 1998, SPIE

    Miriam Leeser

  95. Rothko: a three-dimensional FPGA

    Article • IEEE Design and Test of Computers, January 1998, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  96. Division and square root: choosing the right implementation

    Article • IEEE Micro, January 1997, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  97. Optimizing the data cache performance of a software MPEG-2 video decoder

    Article • January 1997, ACM (Association for Computing Machinery)

    Miriam Leeser

  98. Rothko: A three dimensional FPGA architecture, its fabrication, and design tools

    Article • January 1997, Springer Science + Business Media

    Miriam Leeser

  99. Area and performance tradeoffs in floating-point divide and square-root implementations

    Article • ACM Computing Surveys, September 1996, ACM (Association for Computing Machinery)

    Miriam Leeser

  100. An automaton model for scheduling constraints in synchronous machines

    Article • IEEE Transactions on Computers, January 1995, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  101. Non-restoring integer square root: A case study in design by principled optimization

    Article • January 1995, Springer Science + Business Media

    Miriam Leeser

  102. Reasoning about pipelines with structural hazards

    Article • January 1995, Springer Science + Business Media

    Miriam Leeser

  103. Verifying a logic-synthesis algorithm and implementation: a case study in software verification

    Article • IEEE Transactions on Software Engineering, January 1995, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  104. A methodology for efficient hardware verification

    Article • Formal Methods in System Design, July 1994, Springer Science + Business Media

    Miriam Leeser

  105. PBS: proven Boolean simplification

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April 1994, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  106. Erratum to: High level synthesis and generation FPGAs with the BEDROC system

    Article • The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, December 1993, Springer Science + Business Media

    Miriam Leeser

  107. High level synthesis and generating FPGAs with the BEDROC system

    Article • The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, August 1993, Springer Science + Business Media

    Miriam Leeser

  108. Formally verified synthesis of combinational CMOS circuits

    Article • Integration, June 1991, Elsevier

    Miriam Leeser

  109. From programs to transistors: Verifying hardware synthesis tools

    Article • January 1990, Springer Science + Business Media

    Miriam Leeser

  110. Reasoning about the function and timing of integrated circuits with interval temporal logic

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 1989, Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  111. Automatic determination of signal flow through MOS transistor networks

    Article • Integration, March 1986, Elsevier

    Miriam Leeser

  112. Runtime assignment of reconfigurable hardware components for image processing pipelines

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  113. Run-time execution of reconfigurable hardware in a Java environment

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  114. Design tradeoffs in a hardware implementation of the k-means clustering algorithm

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  115. High level synthesis for designing custom computing hardware

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser

  116. Truly rapid prototyping requires high level synthesis

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Miriam Leeser