All Stories

  1. High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T xor-xnor Cell

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, January 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Mr. Mayur Agarwal

  2. An IEEE Single Precision Floating Point Arithmetic-Based Apodization Architecture for Portable Ultrasound Imaging System

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, June 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Mr. Mayur Agarwal

  3. VLSI architecture for IEEE single precision floating point moving average calculator

    Article • April 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Mr. Mayur Agarwal

  4. Delay Calculator Architecture for Ultrasound Beamformer

    Article • IET Circuits Devices & Systems, July 2016, the Institution of Engineering and Technology (the IET)

    Mr. Mayur Agarwal

  5. A new design of low power high speed hybrid CMOS full adder

    Article • February 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mr. Mayur Agarwal