All Stories

  1. Affinity-Based Thread and Data Mapping in Shared Memory Systems

    Article • ACM Computing Surveys, December 2017, ACM (Association for Computing Machinery)

    Dr Matthias Diener

  2. Strategies to Improve the Performance of a Geophysics Model for Different Manycore Systems

    Article • October 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  3. Data mining the memory access stream to detect anomalous application behavior

    Article • January 2017, ACM (Association for Computing Machinery)

    Dr Matthias Diener

  4. HPC Application Performance and Cost Efficiency in the Cloud

    Article • January 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  5. Leveraging Cloud Heterogeneity for Cost-Efficient Execution of Parallel Applications

    Article • January 2017, Springer Science + Business Media

    Dr Matthias Diener

  6. Optimizing memory affinity with a hybrid compiler/OS approach

    Article • January 2017, ACM (Association for Computing Machinery)

    Dr Matthias Diener

  7. Performance Evaluation of Multiple Cloud Data Centers Allocations for HPC

    Article • January 2017, Springer Science + Business Media

    Dr Matthias Diener

  8. Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures

    Article • ACM Transactions on Architecture and Code Optimization, September 2016, ACM (Association for Computing Machinery)

    Dr Matthias Diener

  9. Kernel-Based Thread and Data Mapping for Improved Memory Affinity

    Article • IEEE Transactions on Parallel and Distributed Systems, September 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  10. A dynamic block-level execution profiler

    Article • Parallel Computing, May 2016, Elsevier

    Dr Matthias Diener

  11. LAPT: A locality-aware page table for thread and data mapping

    Article • Parallel Computing, May 2016, Elsevier

    Dr Matthias Diener

  12. Automatic Communication Optimization of Parallel Applications in Public Clouds

    Article • May 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  13. Modeling memory access behavior for data mapping

    Article • The International Journal of High Performance Computing Applications, April 2016, SAGE Publications

    Dr Matthias Diener

  14. Analyzing and Improving Memory Access Patterns of Large Irregular Applications on NUMA Machines

    Article • February 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  15. Communication in Shared Memory: Concepts, Definitions, and Efficient Detection

    Article • February 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  16. Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency

    Article • February 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  17. A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

    Article • January 2016, Springer Science + Business Media

    Dr Matthias Diener

  18. Opportunities and Challenges of Performing Vector Operations inside the DRAM

    Article • October 2015, ACM (Association for Computing Machinery)

    Dr Matthias Diener

  19. Saving memory movements through vector processing in the DRAM

    Article • October 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  20. SiNUCA: A Validated Micro-Architecture Simulator

    Article • August 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  21. Characterizing communication and page usage of parallel applications for thread and data mapping

    Article • Performance Evaluation, June 2015, Elsevier

    Dr Matthias Diener

  22. Reconfigurable Vector Extensions inside the DRAM

    Article • June 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  23. Communication-aware thread mapping using the translation lookaside buffer

    Article • Concurrency and Computation Practice and Experience, April 2015, Wiley

    Dr Matthias Diener

  24. Partial coscheduling of virtual machines based on memory access patterns

    Article • April 2015, ACM (Association for Computing Machinery)

    Dr Matthias Diener

  25. An Efficient Algorithm for Communication-Based Task Mapping

    Article • March 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  26. Communication-aware process and thread mapping using online communication detection

    Article • Parallel Computing, March 2015, Elsevier

    Dr Matthias Diener

  27. Locality vs. Balance: Exploring Data Mapping Policies on NUMA Systems

    Article • March 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  28. Locality and Balance for Communication-Aware Thread Mapping in Multicore Systems

    Article • January 2015, Springer Science + Business Media

    Dr Matthias Diener

  29. TABARNAC

    Article • January 2015, ACM (Association for Computing Machinery)

    Dr Matthias Diener

  30. Optimizing Memory Locality Using a Locality-Aware Page Table

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  31. Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  32. Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols

    Article • Journal of Parallel and Distributed Computing, March 2014, Elsevier

    Dr Matthias Diener

  33. kMAF

    Article • January 2014, ACM (Association for Computing Machinery)

    Dr Matthias Diener

  34. Energy Efficient Last Level Caches via Last Read/Write Prediction

    Article • October 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  35. Communication-Based Mapping Using Shared Pages

    Article • May 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  36. Analyzing resource interdependencies in multi-core architectures to improve scheduling decisions

    Article • January 2013, ACM (Association for Computing Machinery)

    Dr Matthias Diener

  37. High Performance Computing in the cloud: Deployment, performance and cost efficiency

    Article • December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  38. Evaluating High Performance Computing on the Windows Azure Platform

    Article • June 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  39. Using the Translation Lookaside Buffer to Map Threads in Parallel Applications Based on Shared Memory

    Article • May 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  40. Trace-Based Visualization as a Tool to Understand Applications' I/O Performance in Multi-core Machines

    Article • October 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener

  41. Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors

    Article • September 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Matthias Diener