All Stories

  1. NoXLock: SiP Activation and Licensing through Obfuscated on-Chip Network and Fuzzy Traffic
  2. GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package
  3. SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented Estimation
  4. FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection
  5. Heterogeneous Integration Supply Chain Integrity through Blockchain and CHSM
  6. ActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs
  7. Microelectronics Security in CHIPS Era
  8. FPIC: A Novel Semantic Dataset for Optical PCB Assurance
  9. Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle
  10. SecHLS
  11. SHarPen
  12. RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems
  13. Analyzing Security Vulnerabilities Induced by High-level Synthesis
  14. O'clock
  15. PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation
  16. HLock: Locking IPs at the High-Level Language
  17. CONCEALING-Gate: Optical Contactless Probing Resilient Design
  18. Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks
  19. The Big Hack Explained
  20. Soft-HaT
  21. Permutation Network De-obfuscation
  22. Leveraging Side-Channel Information for Disassembly and Security
  23. Hidden in Plaintext
  24. Electronics Supply Chain Integrity Enabled by Blockchain
  25. LPN-based Device Authentication Using Resistive Memory
  26. Standardizing Bad Cryptographic Practice
  27. ASHES 2017
  28. CDTA
  29. Comparative Analysis of Hardware Obfuscation for IP Protection
  30. Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication
  31. Hardware Trojans
  32. Chip editor
  33. AVFSM
  34. FORTIS