All Stories

  1. Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
  2. RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures
  3. Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability
  4. Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
  5. Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches
  6. ERIC: An Efficient and Practical Software Obfuscation Framework
  7. Low power memristive gas sensor architectures with improved sensing accuracy
  8. Novel Applications Enabled by Memristors [Guest Editorial]
  9. Neutron irradiated perovskite films and solar cells on PET substrates
  10. A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability
  11. A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses
  12. Reliability Assessment of Memristor based Gas Sensor Array
  13. A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations
  14. Soft Error Tolerant Count Min Sketches
  15. A memristor-based sensing and repair system for photovoltaic modules
  16. Guest Editorial: IEEE Transactions on Emerging Topics in Computing Special Issue on Advanced Command, Control and On-Board Data Processing for Space Avionic Systems
  17. Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations
  18. Foreword
  19. Investigation of hysteresis in hole transport layer free metal halide perovskites cells under dark conditions
  20. Characterisation & modelling of perovskite-based synaptic memristor device
  21. Yield Estimation of a Memristive Sensor Array
  22. A Microprocessor Protection Architecture against Hardware Trojans in Memories
  23. On-Board Satellite Telemetry Forecasting with RNN on RISC-V Based Multicore Processor
  24. Characterization of a RISC-V Microcontroller Through Fault Injection
  25. Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing
  26. Fault Modeling and Simulation of Memristor based Gas Sensors
  27. The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors
  28. Design and Implementation of a Flexible Interface for TID Detector
  29. Full characterization of a compact 90Sr/90Y beta source for TID radiation testing
  30. Perovskite based Low Power Synaptic Memristor Device for Neuromorphic application
  31. Memristor Based Planar Tunable RF Circuits
  32. The Case for RISC-V in Space
  33. Towards defining a simplified procedure for COTS system-on-chip TID testing
  34. 45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control
  35. Complementary Resistive Switch Sensing
  36. Foreword
  37. Neutron irradiation of an ARM Cortex-M0 Core
  38. Opcode vector: An efficient scheme to detect soft errors in instructions
  39. Simplified Procedures for COTS TID Testing: A Comparison Between 90Sr and 60Co
  40. Efficient sensing approaches for high-density memristor sensor array
  41. Memristor based adaptive impedance and frequency tuning network
  42. Guest Editorial: <italic>IEEE Transactions on Emerging Topics in Computing</italic> Special Issue on Design & Technology of Integrated Systems in Deep Submicron Era
  43. Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility
  44. Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering
  45. A Double Error Correction Code for 32-Bit Data Words With Efficent Decoding
  46. Dependable Multicore Architectures at Nanoscale
  47. Detecting errors in instructions with bloom filters
  48. High-energy neutrons characterization of a safety critical computing system
  49. Racetrack Logic
  50. Reliable gas sensing with memristive array
  51. Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures
  52. Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures
  53. Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams
  54. A novel method for SEE validation of complex SoCs using Low-Energy Proton beams
  55. Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications
  56. Qualitative techniques for System-on-Chip test with low-energy protons
  57. Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication
  58. A method to protect Bloom filters from soft errors
  59. Characterization of low power radiation-hard reed-solomon code protected serializers in 65-nm for HEP experiments electronics
  60. Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation
  61. Fault detection and repair of DSC arrays through memristor sensing
  62. Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes
  63. 2T2M memristor based TCAM cell for low power applications
  64. Dependable Multicore Architectures at Nanoscale: The View From Europe
  65. A Synergetic Use of Bloom Filters for Error Detection and Correction
  66. Novel Complementary Resistive Switch Crossbar Memory Write and Read Schemes
  67. Lifetime Reliability Analysis of Complementary Resistive Switches Under Threshold and Doping Interface Speed Variations
  68. Total Ionizing Dose Effects on DRAM Data Retention Time
  69. Characterization of data retention faults in DRAM devices
  70. [Front matter]
  71. Using memristor state change behavior to identify faults in photovoltaic arrays
  72. FastTag: A Technique to Protect Cache Tags Against Soft Errors
  73. A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes
  74. Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing
  75. Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset
  76. A 20 mW, 4.8 Gbit/sec, SEU robust serializer in 65nm for read-out of data from LHC experiments
  77. Complementary resistive switch based stateful logic operations using material implication
  78. Efficient implementation of error correction codes in hash tables
  79. F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments
  80. Reducing the Cost of Single Error Correction With Parity Sharing
  81. Introduction to the Special Section
  82. Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories
  83. Error Detection and Correction in Content Addressable Memories by Using Bloom Filters
  84. A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only
  85. High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies
  86. On the design of two single event tolerant slave latches for scan delay testing
  87. Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscale
  88. Low-cost single error correction multiple adjacent error correction codes
  89. Partially Reversible Pipelined QCA Circuits: Combining Low Power With High Throughput
  90. On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS
  91. Error Detection and Correction in Content Addressable Memories
  92. Modeling Open Defects in Nanometric Scale CMOS
  93. High throughput and low power dissipation in QCA pipelines using Bennett clocking
  94. Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits
  95. A Serial Memory by Quantum-Dot Cellular Automata (QCA)
  96. Analysis and Evaluations of Reliability of Reconfigurable FPGAs
  97. Two-Dimensional Schemes for Clocking/Timing of QCA Circuits
  98. On the Error Effects of Random Clock Shifts in Quantum-dot Cellular Automata Circuits
  99. QCA Circuits for Robust Coplanar Crossing
  100. Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers
  101. Evaluating the Yield of Repairable SRAMs for ATE
  102. HDLQ
  103. Reliability Evaluation of Repairable/Reconfigurable FPGAs
  104. Fault localization, error correction, and graceful degradation in radix 2 signed digit-based adders
  105. QCA memory with parallel read∕serial write: design and analysis
  106. A Line-Based Parallel Memory for QCA Implementation
  107. Fault tolerant solid state mass memory for space applications
  108. Tile-based QCA design using majority-like logic primitives
  109. A Comparative Evaluation of Designs for Reliable Memory Systems
  110. Estimating the Manufacturing Yield of Compiler-Based Embedded SRAMs
  111. Markov models of fault-tolerant memory systems under SEU
  112. Design of a fault tolerant solid state mass memory
  113. Localization of Faults in Radix-n Signed Digit Adders
  114. Design of a QCA Memory with Parallel Read/Serial Write
  115. Evaluating the Data Integrity of Memory Systems by Configurable Markov Models
  116. Novel memory designs for QCA implementation
  117. On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories
  118. A fault-tolerant solid state mass memory for highly reliable instrumentation
  119. A signed digit adder with error correction and graceful degradation capabilities
  120. On the yield of compiler-based eSRAMs
  121. Yield evaluation methods of SRAM arrays: a comparative study
  122. Bit flip injection in processor-based architectures: a case study
  123. Development of a dynamic routing system for a fault tolerant solid state mass memory