All Stories

  1. A Single-Cycle, Area-Efficient Calibration Method for TDC-based Timing Monitors
  2. Efficient Hash-to-Index via Rejection Sampling for Online Fault Detection with Bloom/Cuckoo Filters
  3. AMPEREISH: Approximate Multipliers for Power Efficiency in FPGA Designs Using Internal-Self-Healing
  4. Instruction Error Detection with Bloom Filters: Architecture, Radiation Testing and Fault Injection
  5. Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28-nm RISC-V-Based SoC
  6. Memristor based Gas Sensor: Sensitivity and Timing Analysis
  7. Bloom Filters for Soft Error Detection: Neutron and Fault Injection Validation
  8. Neutron Resilience of Flexible Perovskite Solar Cells Using PTAA‐Derived Hole Transport Layers
  9. The online reconfiguration of a distributed on-board computer: The time and network behaviour of a dependable scheduling algorithm
  10. TrackScorer: Skyrmion Logic-in-Memory Accelerator for Tree-Based Ranking Models
  11. From Ground to Orbit: A Robust and Efficient Test Methodology for RISC-V Soft-Cores
  12. Towards Approximate Computing for Deep Learning in Embedded Systems – A Systematic Literature Review
  13. An Enhanced Fault Injection Framework for FPGA-Based Soft-Cores
  14. An Experimental Comparison of RISC-V Processors: Performance, Power, Area and Security - Special Session Paper-
  15. Divertor Tokamak Test facility project: status of design and implementation
  16. Neutron Beam Evaluation of Probabilistic Data Structure-based Online Checkers
  17. Towards the Online Reconfiguration of a Dependable Distributed On-Board Computer
  18. Computer Security – ESORICS 2023
  19. Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses
  20. Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes
  21. Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs
  22. Towards Dependable RISC-V Cores for Edge Computing Devices
  23. An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?
  24. DEV-PIM: Dynamic Execution Validation with Processing-in-Memory
  25. Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
  26. Preventing Soft Errors and Hardware Trojans in RISC-V Cores
  27. Is RISC-V ready for Space? A Security Perspective
  28. RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures
  29. Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability
  30. Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
  31. Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches
  32. ERIC: An Efficient and Practical Software Obfuscation Framework
  33. Low power memristive gas sensor architectures with improved sensing accuracy
  34. Novel Applications Enabled by Memristors [Guest Editorial]
  35. Neutron irradiated perovskite films and solar cells on PET substrates
  36. A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability
  37. A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses
  38. Reliability Assessment of Memristor based Gas Sensor Array
  39. A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations
  40. Soft Error Tolerant Count Min Sketches
  41. A memristor-based sensing and repair system for photovoltaic modules
  42. Guest Editorial: IEEE Transactions on Emerging Topics in Computing Special Issue on Advanced Command, Control and On-Board Data Processing for Space Avionic Systems
  43. Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations
  44. Foreword
  45. Investigation of hysteresis in hole transport layer free metal halide perovskites cells under dark conditions
  46. Characterisation & modelling of perovskite-based synaptic memristor device
  47. Yield Estimation of a Memristive Sensor Array
  48. A Microprocessor Protection Architecture against Hardware Trojans in Memories
  49. On-Board Satellite Telemetry Forecasting with RNN on RISC-V Based Multicore Processor
  50. Characterization of a RISC-V Microcontroller Through Fault Injection
  51. Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing
  52. Fault Modeling and Simulation of Memristor based Gas Sensors
  53. The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors
  54. Design and Implementation of a Flexible Interface for TID Detector
  55. Full characterization of a compact 90Sr/90Y beta source for TID radiation testing
  56. Perovskite based Low Power Synaptic Memristor Device for Neuromorphic application
  57. Memristor Based Planar Tunable RF Circuits
  58. The Case for RISC-V in Space
  59. Towards defining a simplified procedure for COTS system-on-chip TID testing
  60. 45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control
  61. Complementary Resistive Switch Sensing
  62. Foreword
  63. Neutron irradiation of an ARM Cortex-M0 Core
  64. Opcode vector: An efficient scheme to detect soft errors in instructions
  65. Simplified Procedures for COTS TID Testing: A Comparison Between 90Sr and 60Co
  66. Efficient sensing approaches for high-density memristor sensor array
  67. Memristor based adaptive impedance and frequency tuning network
  68. Guest Editorial: <italic>IEEE Transactions on Emerging Topics in Computing</italic> Special Issue on Design & Technology of Integrated Systems in Deep Submicron Era
  69. Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility
  70. Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering
  71. A Double Error Correction Code for 32-Bit Data Words With Efficent Decoding
  72. Dependable Multicore Architectures at Nanoscale
  73. Detecting errors in instructions with bloom filters
  74. High-energy neutrons characterization of a safety critical computing system
  75. Racetrack Logic
  76. Reliable gas sensing with memristive array
  77. Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures
  78. Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures
  79. Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams
  80. A novel method for SEE validation of complex SoCs using Low-Energy Proton beams
  81. Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications
  82. Qualitative techniques for System-on-Chip test with low-energy protons
  83. Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication
  84. A method to protect Bloom filters from soft errors
  85. Characterization of low power radiation-hard reed-solomon code protected serializers in 65-nm for HEP experiments electronics
  86. Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation
  87. Fault detection and repair of DSC arrays through memristor sensing
  88. Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes
  89. 2T2M memristor based TCAM cell for low power applications
  90. Dependable Multicore Architectures at Nanoscale: The View From Europe
  91. A Synergetic Use of Bloom Filters for Error Detection and Correction
  92. Novel Complementary Resistive Switch Crossbar Memory Write and Read Schemes
  93. Lifetime Reliability Analysis of Complementary Resistive Switches Under Threshold and Doping Interface Speed Variations
  94. Total Ionizing Dose Effects on DRAM Data Retention Time
  95. Characterization of data retention faults in DRAM devices
  96. [Front matter]
  97. Using memristor state change behavior to identify faults in photovoltaic arrays
  98. FastTag: A Technique to Protect Cache Tags Against Soft Errors
  99. A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes
  100. Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing
  101. Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset
  102. A 20 mW, 4.8 Gbit/sec, SEU robust serializer in 65nm for read-out of data from LHC experiments
  103. Complementary resistive switch based stateful logic operations using material implication
  104. Efficient implementation of error correction codes in hash tables
  105. Complementary resistive switch based stateful logic operations using material implication
  106. F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments
  107. Reducing the Cost of Single Error Correction With Parity Sharing
  108. Introduction to the Special Section
  109. Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories
  110. Error Detection and Correction in Content Addressable Memories by Using Bloom Filters
  111. A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only
  112. Error Detection in Ternary CAMs Using Bloom Filters
  113. High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies
  114. On the design of two single event tolerant slave latches for scan delay testing
  115. Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscale
  116. Low-cost single error correction multiple adjacent error correction codes
  117. Partially Reversible Pipelined QCA Circuits: Combining Low Power With High Throughput
  118. On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS
  119. Modeling magnetic quantum-dot cellular automata by HDL
  120. Feedback based droop mitigation
  121. Error Detection and Correction in Content Addressable Memories
  122. Modeling Open Defects in Nanometric Scale CMOS
  123. High throughput and low power dissipation in QCA pipelines using Bennett clocking
  124. Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits
  125. A Serial Memory by Quantum-Dot Cellular Automata (QCA)
  126. Analysis and Evaluations of Reliability of Reconfigurable FPGAs
  127. Two-Dimensional Schemes for Clocking/Timing of QCA Circuits
  128. On the Error Effects of Random Clock Shifts in Quantum-dot Cellular Automata Circuits
  129. QCA Circuits for Robust Coplanar Crossing
  130. Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers
  131. Evaluating the Yield of Repairable SRAMs for ATE
  132. HDLQ
  133. Reliability Evaluation of Repairable/Reconfigurable FPGAs
  134. Fault localization, error correction, and graceful degradation in radix 2 signed digit-based adders
  135. QCA memory with parallel read∕serial write: design and analysis
  136. Novel designs for thermally robust coplanar crossing in QCA
  137. Timing Verification of QCA Memory Architectures
  138. Clocking and Cell Placement for QCA
  139. A Line-Based Parallel Memory for QCA Implementation
  140. Fault tolerant solid state mass memory for space applications
  141. Tile-based QCA design using majority-like logic primitives
  142. A Comparative Evaluation of Designs for Reliable Memory Systems
  143. Estimating the Manufacturing Yield of Compiler-Based Embedded SRAMs
  144. Tile-based design of a serial memory in QCA
  145. Simulation of reconfigurable memory core yield
  146. Markov models of fault-tolerant memory systems under SEU
  147. Design of a fault tolerant solid state mass memory
  148. Localization of Faults in Radix-n Signed Digit Adders
  149. Design of a QCA Memory with Parallel Read/Serial Write
  150. Evaluating the Data Integrity of Memory Systems by Configurable Markov Models
  151. Novel memory designs for QCA implementation
  152. On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories
  153. A fault-tolerant solid state mass memory for highly reliable instrumentation
  154. A signed digit adder with error correction and graceful degradation capabilities
  155. On the yield of compiler-based eSRAMs
  156. Yield evaluation methods of SRAM arrays: a comparative study
  157. Bit flip injection in processor-based architectures: a case study
  158. Development of a dynamic routing system for a fault tolerant solid state mass memory
  159. Modeling QCA defects at molecular-level in combinational circuits
  160. Data integrity evaluations of reed solomon codes for storage systems
  161. Testing of inter-word coupling faults in word-oriented SRAMs
  162. Error detection in signed digit arithmetic circuit with parity checker [adder example]
  163. A fault tolerant hardware based file system manager for solid state mass memory
  164. Yield analysis of compiler-based arrays of embedded SRAMs
  165. A self-checking cell logic block for fault tolerant FPGAs
  166. System-on-chip oriented fault-tolerant sequential systems implementation methodology
  167. A fault-tolerant 176 Gbit solid state mass memory architecture