All Stories

  1. AMPEREISH: Approximate Multipliers for Power Efficiency in FPGA Designs Using Internal-Self-Healing
  2. Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28-nm RISC-V-Based SoC
  3. Memristor based Gas Sensor: Sensitivity and Timing Analysis
  4. Bloom Filters for Soft Error Detection: Neutron and Fault Injection Validation
  5. Neutron Resilience of Flexible Perovskite Solar Cells Using PTAA‐Derived Hole Transport Layers
  6. The online reconfiguration of a distributed on-board computer: The time and network behaviour of a dependable scheduling algorithm
  7. TrackScorer: Skyrmion Logic-in-Memory Accelerator for Tree-Based Ranking Models
  8. From Ground to Orbit: A Robust and Efficient Test Methodology for RISC-V Soft-Cores
  9. Towards Approximate Computing for Deep Learning in Embedded Systems – A Systematic Literature Review
  10. An Enhanced Fault Injection Framework for FPGA-Based Soft-Cores
  11. An Experimental Comparison of RISC-V Processors: Performance, Power, Area and Security - Special Session Paper-
  12. Divertor Tokamak Test facility project: status of design and implementation
  13. Neutron Beam Evaluation of Probabilistic Data Structure-based Online Checkers
  14. Towards the Online Reconfiguration of a Dependable Distributed On-Board Computer
  15. Computer Security – ESORICS 2023
  16. Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses
  17. Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes
  18. Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs
  19. Towards Dependable RISC-V Cores for Edge Computing Devices
  20. An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?
  21. DEV-PIM: Dynamic Execution Validation with Processing-in-Memory
  22. Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
  23. Preventing Soft Errors and Hardware Trojans in RISC-V Cores
  24. Is RISC-V ready for Space? A Security Perspective
  25. RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures
  26. Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability
  27. Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
  28. Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches
  29. ERIC: An Efficient and Practical Software Obfuscation Framework
  30. Low power memristive gas sensor architectures with improved sensing accuracy
  31. Novel Applications Enabled by Memristors [Guest Editorial]
  32. Neutron irradiated perovskite films and solar cells on PET substrates
  33. A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability
  34. A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses
  35. Reliability Assessment of Memristor based Gas Sensor Array
  36. A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations
  37. Soft Error Tolerant Count Min Sketches
  38. A memristor-based sensing and repair system for photovoltaic modules
  39. Guest Editorial: IEEE Transactions on Emerging Topics in Computing Special Issue on Advanced Command, Control and On-Board Data Processing for Space Avionic Systems
  40. Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations
  41. Foreword
  42. Investigation of hysteresis in hole transport layer free metal halide perovskites cells under dark conditions
  43. Characterisation & modelling of perovskite-based synaptic memristor device
  44. Yield Estimation of a Memristive Sensor Array
  45. A Microprocessor Protection Architecture against Hardware Trojans in Memories
  46. On-Board Satellite Telemetry Forecasting with RNN on RISC-V Based Multicore Processor
  47. Characterization of a RISC-V Microcontroller Through Fault Injection
  48. Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing
  49. Fault Modeling and Simulation of Memristor based Gas Sensors
  50. The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors
  51. Design and Implementation of a Flexible Interface for TID Detector
  52. Full characterization of a compact 90Sr/90Y beta source for TID radiation testing
  53. Perovskite based Low Power Synaptic Memristor Device for Neuromorphic application
  54. Memristor Based Planar Tunable RF Circuits
  55. The Case for RISC-V in Space
  56. Towards defining a simplified procedure for COTS system-on-chip TID testing
  57. 45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control
  58. Complementary Resistive Switch Sensing
  59. Foreword
  60. Neutron irradiation of an ARM Cortex-M0 Core
  61. Opcode vector: An efficient scheme to detect soft errors in instructions
  62. Simplified Procedures for COTS TID Testing: A Comparison Between 90Sr and 60Co
  63. Efficient sensing approaches for high-density memristor sensor array
  64. Memristor based adaptive impedance and frequency tuning network
  65. Guest Editorial: <italic>IEEE Transactions on Emerging Topics in Computing</italic> Special Issue on Design & Technology of Integrated Systems in Deep Submicron Era
  66. Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility
  67. Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering
  68. A Double Error Correction Code for 32-Bit Data Words With Efficent Decoding
  69. Dependable Multicore Architectures at Nanoscale
  70. Detecting errors in instructions with bloom filters
  71. High-energy neutrons characterization of a safety critical computing system
  72. Racetrack Logic
  73. Reliable gas sensing with memristive array
  74. Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures
  75. Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures
  76. Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams
  77. A novel method for SEE validation of complex SoCs using Low-Energy Proton beams
  78. Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications
  79. Qualitative techniques for System-on-Chip test with low-energy protons
  80. Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication
  81. A method to protect Bloom filters from soft errors
  82. Characterization of low power radiation-hard reed-solomon code protected serializers in 65-nm for HEP experiments electronics
  83. Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation
  84. Fault detection and repair of DSC arrays through memristor sensing
  85. Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes
  86. 2T2M memristor based TCAM cell for low power applications
  87. Dependable Multicore Architectures at Nanoscale: The View From Europe
  88. A Synergetic Use of Bloom Filters for Error Detection and Correction
  89. Novel Complementary Resistive Switch Crossbar Memory Write and Read Schemes
  90. Lifetime Reliability Analysis of Complementary Resistive Switches Under Threshold and Doping Interface Speed Variations
  91. Total Ionizing Dose Effects on DRAM Data Retention Time
  92. Characterization of data retention faults in DRAM devices
  93. [Front matter]
  94. Using memristor state change behavior to identify faults in photovoltaic arrays
  95. FastTag: A Technique to Protect Cache Tags Against Soft Errors
  96. A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes
  97. Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing
  98. Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset
  99. A 20 mW, 4.8 Gbit/sec, SEU robust serializer in 65nm for read-out of data from LHC experiments
  100. Complementary resistive switch based stateful logic operations using material implication
  101. Efficient implementation of error correction codes in hash tables
  102. Complementary resistive switch based stateful logic operations using material implication
  103. F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments
  104. Reducing the Cost of Single Error Correction With Parity Sharing
  105. Introduction to the Special Section
  106. Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories
  107. Error Detection and Correction in Content Addressable Memories by Using Bloom Filters
  108. A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only
  109. Error Detection in Ternary CAMs Using Bloom Filters
  110. High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies
  111. On the design of two single event tolerant slave latches for scan delay testing
  112. Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscale
  113. Low-cost single error correction multiple adjacent error correction codes
  114. Partially Reversible Pipelined QCA Circuits: Combining Low Power With High Throughput
  115. On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS
  116. Modeling magnetic quantum-dot cellular automata by HDL
  117. Feedback based droop mitigation
  118. Error Detection and Correction in Content Addressable Memories
  119. Modeling Open Defects in Nanometric Scale CMOS
  120. High throughput and low power dissipation in QCA pipelines using Bennett clocking
  121. Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits
  122. A Serial Memory by Quantum-Dot Cellular Automata (QCA)
  123. Analysis and Evaluations of Reliability of Reconfigurable FPGAs
  124. Two-Dimensional Schemes for Clocking/Timing of QCA Circuits
  125. On the Error Effects of Random Clock Shifts in Quantum-dot Cellular Automata Circuits
  126. QCA Circuits for Robust Coplanar Crossing
  127. Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers
  128. Evaluating the Yield of Repairable SRAMs for ATE
  129. HDLQ
  130. Reliability Evaluation of Repairable/Reconfigurable FPGAs
  131. Fault localization, error correction, and graceful degradation in radix 2 signed digit-based adders
  132. QCA memory with parallel read∕serial write: design and analysis
  133. Novel designs for thermally robust coplanar crossing in QCA
  134. Timing Verification of QCA Memory Architectures
  135. Clocking and Cell Placement for QCA
  136. A Line-Based Parallel Memory for QCA Implementation
  137. Fault tolerant solid state mass memory for space applications
  138. Tile-based QCA design using majority-like logic primitives
  139. A Comparative Evaluation of Designs for Reliable Memory Systems
  140. Estimating the Manufacturing Yield of Compiler-Based Embedded SRAMs
  141. Tile-based design of a serial memory in QCA
  142. Simulation of reconfigurable memory core yield
  143. Markov models of fault-tolerant memory systems under SEU
  144. Design of a fault tolerant solid state mass memory
  145. Localization of Faults in Radix-n Signed Digit Adders
  146. Design of a QCA Memory with Parallel Read/Serial Write
  147. Evaluating the Data Integrity of Memory Systems by Configurable Markov Models
  148. Novel memory designs for QCA implementation
  149. On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories
  150. A fault-tolerant solid state mass memory for highly reliable instrumentation
  151. A signed digit adder with error correction and graceful degradation capabilities
  152. On the yield of compiler-based eSRAMs
  153. Yield evaluation methods of SRAM arrays: a comparative study
  154. Bit flip injection in processor-based architectures: a case study
  155. Development of a dynamic routing system for a fault tolerant solid state mass memory
  156. Modeling QCA defects at molecular-level in combinational circuits
  157. Data integrity evaluations of reed solomon codes for storage systems
  158. Testing of inter-word coupling faults in word-oriented SRAMs
  159. Error detection in signed digit arithmetic circuit with parity checker [adder example]
  160. A fault tolerant hardware based file system manager for solid state mass memory
  161. Yield analysis of compiler-based arrays of embedded SRAMs
  162. A self-checking cell logic block for fault tolerant FPGAs
  163. System-on-chip oriented fault-tolerant sequential systems implementation methodology
  164. A fault-tolerant 176 Gbit solid state mass memory architecture