All Stories

  1. Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28-nm RISC-V-Based SoC
  2. Memristor based Gas Sensor: Sensitivity and Timing Analysis
  3. Bloom Filters for Soft Error Detection: Neutron and Fault Injection Validation
  4. Neutron Resilience of Flexible Perovskite Solar Cells Using PTAA‐Derived Hole Transport Layers
  5. The online reconfiguration of a distributed on-board computer: The time and network behaviour of a dependable scheduling algorithm
  6. TrackScorer: Skyrmion Logic-in-Memory Accelerator for Tree-Based Ranking Models
  7. From Ground to Orbit: A Robust and Efficient Test Methodology for RISC-V Soft-Cores
  8. Towards Approximate Computing for Deep Learning in Embedded Systems – A Systematic Literature Review
  9. An Enhanced Fault Injection Framework for FPGA-Based Soft-Cores
  10. An Experimental Comparison of RISC-V Processors: Performance, Power, Area and Security - Special Session Paper-
  11. Divertor Tokamak Test facility project: status of design and implementation
  12. Neutron Beam Evaluation of Probabilistic Data Structure-based Online Checkers
  13. Towards the Online Reconfiguration of a Dependable Distributed On-Board Computer
  14. Computer Security – ESORICS 2023
  15. Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses
  16. Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes
  17. Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs
  18. Towards Dependable RISC-V Cores for Edge Computing Devices
  19. An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?
  20. DEV-PIM: Dynamic Execution Validation with Processing-in-Memory
  21. Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
  22. Preventing Soft Errors and Hardware Trojans in RISC-V Cores
  23. Is RISC-V ready for Space? A Security Perspective
  24. RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures
  25. Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability
  26. Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
  27. Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches
  28. ERIC: An Efficient and Practical Software Obfuscation Framework
  29. Low power memristive gas sensor architectures with improved sensing accuracy
  30. Novel Applications Enabled by Memristors [Guest Editorial]
  31. Neutron irradiated perovskite films and solar cells on PET substrates
  32. A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability
  33. A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses
  34. Reliability Assessment of Memristor based Gas Sensor Array
  35. A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations
  36. Soft Error Tolerant Count Min Sketches
  37. A memristor-based sensing and repair system for photovoltaic modules
  38. Guest Editorial: IEEE Transactions on Emerging Topics in Computing Special Issue on Advanced Command, Control and On-Board Data Processing for Space Avionic Systems
  39. Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations
  40. Foreword
  41. Investigation of hysteresis in hole transport layer free metal halide perovskites cells under dark conditions
  42. Characterisation & modelling of perovskite-based synaptic memristor device
  43. Yield Estimation of a Memristive Sensor Array
  44. A Microprocessor Protection Architecture against Hardware Trojans in Memories
  45. On-Board Satellite Telemetry Forecasting with RNN on RISC-V Based Multicore Processor
  46. Characterization of a RISC-V Microcontroller Through Fault Injection
  47. Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing
  48. Fault Modeling and Simulation of Memristor based Gas Sensors
  49. The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors
  50. Design and Implementation of a Flexible Interface for TID Detector
  51. Full characterization of a compact 90Sr/90Y beta source for TID radiation testing
  52. Perovskite based Low Power Synaptic Memristor Device for Neuromorphic application
  53. Memristor Based Planar Tunable RF Circuits
  54. The Case for RISC-V in Space
  55. Towards defining a simplified procedure for COTS system-on-chip TID testing
  56. 45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control
  57. Complementary Resistive Switch Sensing
  58. Foreword
  59. Neutron irradiation of an ARM Cortex-M0 Core
  60. Opcode vector: An efficient scheme to detect soft errors in instructions
  61. Simplified Procedures for COTS TID Testing: A Comparison Between 90Sr and 60Co
  62. Efficient sensing approaches for high-density memristor sensor array
  63. Memristor based adaptive impedance and frequency tuning network
  64. Guest Editorial: <italic>IEEE Transactions on Emerging Topics in Computing</italic> Special Issue on Design & Technology of Integrated Systems in Deep Submicron Era
  65. Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility
  66. Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering
  67. A Double Error Correction Code for 32-Bit Data Words With Efficent Decoding
  68. Dependable Multicore Architectures at Nanoscale
  69. Detecting errors in instructions with bloom filters
  70. High-energy neutrons characterization of a safety critical computing system
  71. Racetrack Logic
  72. Reliable gas sensing with memristive array
  73. Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures
  74. Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures
  75. Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams
  76. A novel method for SEE validation of complex SoCs using Low-Energy Proton beams
  77. Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications
  78. Qualitative techniques for System-on-Chip test with low-energy protons
  79. Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication
  80. A method to protect Bloom filters from soft errors
  81. Characterization of low power radiation-hard reed-solomon code protected serializers in 65-nm for HEP experiments electronics
  82. Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation
  83. Fault detection and repair of DSC arrays through memristor sensing
  84. Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes
  85. 2T2M memristor based TCAM cell for low power applications
  86. Dependable Multicore Architectures at Nanoscale: The View From Europe
  87. A Synergetic Use of Bloom Filters for Error Detection and Correction
  88. Novel Complementary Resistive Switch Crossbar Memory Write and Read Schemes
  89. Lifetime Reliability Analysis of Complementary Resistive Switches Under Threshold and Doping Interface Speed Variations
  90. Total Ionizing Dose Effects on DRAM Data Retention Time
  91. Characterization of data retention faults in DRAM devices
  92. [Front matter]
  93. Using memristor state change behavior to identify faults in photovoltaic arrays
  94. FastTag: A Technique to Protect Cache Tags Against Soft Errors
  95. A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes
  96. Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing
  97. Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset
  98. A 20 mW, 4.8 Gbit/sec, SEU robust serializer in 65nm for read-out of data from LHC experiments
  99. Complementary resistive switch based stateful logic operations using material implication
  100. Efficient implementation of error correction codes in hash tables
  101. Complementary resistive switch based stateful logic operations using material implication
  102. F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments
  103. Reducing the Cost of Single Error Correction With Parity Sharing
  104. Introduction to the Special Section
  105. Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories
  106. Error Detection and Correction in Content Addressable Memories by Using Bloom Filters
  107. A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only
  108. Error Detection in Ternary CAMs Using Bloom Filters
  109. High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies
  110. On the design of two single event tolerant slave latches for scan delay testing
  111. Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscale
  112. Low-cost single error correction multiple adjacent error correction codes
  113. Partially Reversible Pipelined QCA Circuits: Combining Low Power With High Throughput
  114. On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS
  115. Modeling magnetic quantum-dot cellular automata by HDL
  116. Feedback based droop mitigation
  117. Error Detection and Correction in Content Addressable Memories
  118. Modeling Open Defects in Nanometric Scale CMOS
  119. High throughput and low power dissipation in QCA pipelines using Bennett clocking
  120. Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits
  121. A Serial Memory by Quantum-Dot Cellular Automata (QCA)
  122. Analysis and Evaluations of Reliability of Reconfigurable FPGAs
  123. Two-Dimensional Schemes for Clocking/Timing of QCA Circuits
  124. On the Error Effects of Random Clock Shifts in Quantum-dot Cellular Automata Circuits
  125. QCA Circuits for Robust Coplanar Crossing
  126. Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers
  127. Evaluating the Yield of Repairable SRAMs for ATE
  128. HDLQ
  129. Reliability Evaluation of Repairable/Reconfigurable FPGAs
  130. Fault localization, error correction, and graceful degradation in radix 2 signed digit-based adders
  131. QCA memory with parallel read∕serial write: design and analysis
  132. Novel designs for thermally robust coplanar crossing in QCA
  133. Timing Verification of QCA Memory Architectures
  134. Clocking and Cell Placement for QCA
  135. A Line-Based Parallel Memory for QCA Implementation
  136. Fault tolerant solid state mass memory for space applications
  137. Tile-based QCA design using majority-like logic primitives
  138. A Comparative Evaluation of Designs for Reliable Memory Systems
  139. Estimating the Manufacturing Yield of Compiler-Based Embedded SRAMs
  140. Tile-based design of a serial memory in QCA
  141. Simulation of reconfigurable memory core yield
  142. Markov models of fault-tolerant memory systems under SEU
  143. Design of a fault tolerant solid state mass memory
  144. Localization of Faults in Radix-n Signed Digit Adders
  145. Design of a QCA Memory with Parallel Read/Serial Write
  146. Evaluating the Data Integrity of Memory Systems by Configurable Markov Models
  147. Novel memory designs for QCA implementation
  148. On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories
  149. A fault-tolerant solid state mass memory for highly reliable instrumentation
  150. A signed digit adder with error correction and graceful degradation capabilities
  151. On the yield of compiler-based eSRAMs
  152. Yield evaluation methods of SRAM arrays: a comparative study
  153. Bit flip injection in processor-based architectures: a case study
  154. Development of a dynamic routing system for a fault tolerant solid state mass memory
  155. Modeling QCA defects at molecular-level in combinational circuits
  156. Data integrity evaluations of reed solomon codes for storage systems
  157. Testing of inter-word coupling faults in word-oriented SRAMs
  158. Error detection in signed digit arithmetic circuit with parity checker [adder example]
  159. A fault tolerant hardware based file system manager for solid state mass memory
  160. Yield analysis of compiler-based arrays of embedded SRAMs
  161. A self-checking cell logic block for fault tolerant FPGAs
  162. System-on-chip oriented fault-tolerant sequential systems implementation methodology
  163. A fault-tolerant 176 Gbit solid state mass memory architecture