All Stories

  1. Move the Roof: Model-driven Methodology for Designing Efficient Deep Learning Architectures
  2. Interpreting High Order Epistasis Using Sparse Transformers
  3. Transient-Execution Attacks: a Computer Architect Perspective
  4. Temperature-aware Core Management in MPSoCs: Modeling and Evaluation using MRMs
  5. A New Energy-Efficient Hybrid Wide-Operand Adder Architecture
  6. A Survey on Fully Homomorphic Encryption
  7. Adaptive Scheduling Framework for Real-Time Video Encoding on Heterogeneous Systems
  8. $2^n$ RNS Scalers for Extended 4-Moduli Sets
  9. GPU-assisted HEVC intra decoder
  10. Arithmetic-Based Binary-to-RNS Converter Modulo ${\{2^{n}{\pm}k\}}$ for $jn$ -bit Dynamic Range
  11. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
  12. Stretching the limits of Programmable Embedded Devices for Public-key Cryptography
  13. ROM-less RNS-to-binary converter moduli {22n − 1, 22n + 1, 2n − 3, 2n + 3}
  14. Collaborative inter-prediction on CPU+GPU systems
  15. Reconfigurable data flow engine for HEVC motion estimation
  16. On the Evaluation of Multi-core Systems with SIMD Engines for Public-Key Cryptography
  17. Performance-Aware Task Management and Frequency Scaling in Embedded Systems
  18. FEVES: Framework for Efficient Parallel Video Encoding on Heterogeneous Systems
  19. Efficient sign identification engines for integers represented in RNS extended 3-moduli set {2 n − 1, 2 n + k , 2 n + 1}
  20. Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs
  21. Method for designing multi-channel RNS architectures to prevent power analysis SCA
  22. Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era
  23. Cooperative CPU+GPU deblocking filter parallelization for high performance HEVC video codecs
  24. Efficient Multilevel Load Balancing on Heterogeneous CPU + GPU Systems
  25. Design and Optimization of Scientific Applications for Highly Heterogeneous and Hierarchical HPC Platforms Using Functional Computation Performance Models
  26. A Flexible Architecture for Modular Arithmetic Hardware Accelerators based on RNS
  27. An Efficient Scalable RNS Architecture for Large Dynamic Ranges
  28. Cache-aware Roofline model: Upgrading the loft
  29. Finite-Difference in Time-Domain Scalable Implementations on CUDA and OpenCL
  30. Dynamic Load Balancing for Real-Time Video Encoding on Heterogeneous CPU+GPU Systems
  31. EFFICIENT METHOD FOR DESIGNING MODULO {2 n ± k} MULTIPLIERS
  32. SchedMon: A Performance and Energy Monitoring Tool for Modern Multi-cores
  33. Monitoring Performance and Power for Application Characterization with the Cache-Aware Roofline Model
  34. Exploiting Coarse-grained Parallelism in Multi-transform Architectures for H.264/AVC High Profile Codecs
  35. Method to Design General RNS Reverse Converters for Extended Moduli Sets
  36. Open the Gates: Using High-level Synthesis towards programmable LDPC decoders on FPGAs
  37. Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks
  38. A Lab Project on the Design and Implementation of Programmable and Configurable Embedded Systems
  39. A comparison of computing architectures and parallelization frameworks based on a two-dimensional FDTD
  40. Exploiting task and data parallelism for advanced video coding on hybrid CPU + GPU platforms
  41. A compact and scalable RNS architecture
  42. RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to $(8n+1)$ -bit
  43. An RNS-based architecture targeting hardware accelerators for modular arithmetic
  44. Accelerating the Computation of Induced Dipoles for Molecular Mechanics with Dataflow Engines
  45. The CRNS framework and its application to programmable and reconfigurable cryptography
  46. Multi-level Parallelization of Advanced Video Coding on Hybrid CPU+GPU Platforms
  47. Reconfigurable Architecture for Cryptography over Binary Finite Fields
  48. 2-Axis Magnetometers Based on Full Wheatstone Bridges Incorporating Magnetic Tunnel Junctions Connected in Series
  49. Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems
  50. Real-time implementation of remotely sensed hyperspectral image unmixing on GPUs
  51. RNS Arithmetic Units for Modulo {2^n+-k}
  52. VLSI Reverse Converter for RNS Based on the Moduli Set
  53. High Performance Unified Architecture for Forward and Inverse Quantization in H.264/AVC
  54. Fine-grain parallelism using multi-core, Cell/BE, and GPU Systems
  55. Energy efficient stream-based configurable architecture for embedded platforms
  56. Simultaneous Multi-Level Divisible Load Balancing for Heterogeneous Desktop Systems
  57. Computation of Induced Dipoles in Molecular Mechanics Simulations Using Graphics Processors
  58. Corrections to “MRC-Based RNS Reverse Converters for the Four-Moduli Sets $\{2^{n} + 1,\ 2^{n} - 1,\ 2^{n},\ 2^{2n + 1} - 1\}$ and
  59. MRC-Based RNS Reverse Converters for the Four-Moduli Sets $\{2^{n} + 1, 2^{n} - 1, 2^{n}, 2^{2n + 1} - 1\}$ and $ \{2^{n} + 1, 2^{n} - ...
  60. Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design
  61. On Realistic Divisible Load Scheduling in Highly Heterogeneous Distributed Systems
  62. Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion
  63. Scheduling Divisible Loads on Heterogeneous Desktop Systems with Limited Memory
  64. Hierarchical Partitioning Algorithm for Scientific Computing on Highly Heterogeneous CPU + GPU Clusters
  65. A tutorial overview on the properties of the discrete cosine transform for encoded image and video processing
  66. Parallel Computing – Special Issue
  67. Binary-to-RNS Conversion Units for moduli {2^n ± 3}
  68. High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems
  69. Real-time DVB-S2 LDPC decoding on many-core GPU accelerators
  70. Massively LDPC Decoding on Multicore Architectures
  71. Parallel LDPC Decoding
  72. Introduction
  73. A quantitative analysis of firing rate estimators: Unveiling bias sources
  74. Exploiting SIMD extensions for linear image processing with OpenCL
  75. Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems
  76. H.264/AVC framework for multi-core embedded video encoders
  77. Unifying stream based and reconfigurable computing to design application accelerators
  78. An improved RNS generator 2n ± k based on threshold logic
  79. Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations
  80. Embedded multicore architectures for LDPC decoding
  81. Elliptic Curve point multiplication on GPUs
  82. Efficient Independent Component Analysis on a GPU
  83. Challenges and trends in the development of a magnetoresistive biochip portable platform
  84. Programming Cell/BE and GPUs systems for real-time video encoding
  85. Collaborative execution environment for heterogeneous parallel systems
  86. Modeling and Evaluating Non-shared Memory CELL/BE Type Multi-core Architectures for Local Image and Video Processing
  87. Preface
  88. Euro-Par 2009 – Parallel Processing Workshops
  89. Iterative induced dipoles computation for molecular mechanics on GPUs
  90. p264
  91. Development and evaluation of scalable video motion estimators on GPU
  92. Fine-grain Parallelism Using Multi-core, Cell/BE, and GPU Systems: Accelerating the Phylogenetic Likelihood Function
  93. Parallel LDPC Decoding on GPUs Using a Stream-Based Computing Approach
  94. Modelling and programming stream-based distributed computing based on the meta-pipeline approach
  95. How GPUs can outperform ASICs for fast LDPC decoding
  96. Multi-core platforms for signal processing: source and channel coding
  97. Neural code metrics: Analysis and application to the assessment of neural models
  98. CaravelaMPI: Message Passing Interface for Parallel GPU-Based Applications
  99. Distributed Software Platform for Automation and Control of General Anaesthesia
  100. A Portable and Autonomous Magnetic Detection Platform for Biosensing
  101. BIOELECTRONIC VISION
  102. Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices
  103. Bioelectronic Vision
  104. Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study
  105. Parallel LDPC Decoding on the Cell/B.E. Processor
  106. On the design of distributed autonomous embedded systems for biomedical applications
  107. Efficient FPGA elliptic curve cryptographic processor over GF(2m)
  108. Design and implementation of a tool for modeling and programming deadlock free meta-pipeline applications
  109. Merged Computation for Whirlpool Hashing
  110. Edge Stream Oriented LDPC Decoding
  111. On-the-fly attestation of reconfigurable hardware
  112. Merged computation for Whirlpool hashing
  113. A Parallel Algorithm for Advanced Video Motion Estimation on Multicore Architectures
  114. Low power microarchitecture with instruction reuse
  115. Distributed Web-based Platform for Computer Architecture Simulation
  116. Heuristic Optimization Methods for Improving Performance of Recursive General Purpose Applications on GPUs
  117. Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units
  118. An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences
  119. BRAM-LUT Tradeoff on a Polymorphic DES Design
  120. Reconfigurable architectures and processors for real-time video motion estimation
  121. QCA-LG: A tool for the automatic layout generation of QCA combinational circuits
  122. Efficient Hybrid DCT-Domain Algorithm for Video Spatial Downscaling
  123. A Run-Time Reconfigurable Processor for Video Motion Estimation
  124. Meta-Pipeline: A New Execution Mechanism for Distributed Pipeline Processing
  125. Adaptive Motion Estimation Algorithm for H.264/AVC
  126. An Efficient Expectation-Maximisation Algorithm for Spike Classification
  127. An ASIP approach for adaptive AVC Motion Estimation
  128. Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli
  129. Caravela: A Novel Stream-Based Distributed Computing Environment
  130. Additive Logistic Regression Applied to Retina Modelling
  131. Feature Selection for the Stochastic Integrate and Fire Model
  132. Design and implementation of a stream-based distributedcomputing platform using graphics processing units
  133. Data buffering optimization methods toward a uniform programming interface for gpu-based applications
  134. Embedded Systems for Portable and Mobile Video Platforms
  135. A New Hand-Held Microsystem Architecture for Biological Analysis
  136. MAESTRO2: EXPERIMENTAL EVALUATION OF COMMUNICATION PERFORMANCE IMPROVEMENT TECHNIQUES IN THE LINK LAYER
  137. Configurable Embedded Core for Controlling Electro-Mechanical Systems
  138. Improving SHA-2 Hardware Implementations
  139. Rescheduling for Optimized SHA-1 Calculation
  140. Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators
  141. On Task Scheduling Accuracy: Evaluation Methodology and Results
  142. List scheduling: extension for contention awareness and evaluation of node priorities for heterogeneous cluster architectures
  143. A programmable cellular neural network circuit
  144. Fast transcoding architectures for insertion of non-regular shaped objects in the compressed DCT-domain
  145. An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time
  146. Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs
  147. A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation
  148. Synchronous Non-local Image Processing on Orthogonal Multiprocessor Systems
  149. Exploiting Unused Time Slots in List Scheduling Considering Communication Contention
  150. A Platform Independent Parallelising Tool Based on Graph Theoretic Models
  151. Scheduling Task Graphs on Arbitrary Processor Architectures Considering Contention
  152. Customizable and Reduced Hardware Motion Estimation Processors
  153. Massive Data Classification of Neural Responses
  154. Bioinspired Stimulus Encoder for Cortical Visual Neuroprostheses
  155. On the Implementation and Evaluation of Berkeley Sockets on Maestro2 cluster computing environment
  156. Nanotechnology and the Detection of Biomolecular Recognition Using Magnetoresistive Transducers