All Stories

  1. Direction-Constrained Rectangle Escape Routing

    Article • ACM Transactions on Design Automation of Electronic Systems, April 2018, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  2. Layer Assignment of Escape Buses with Consecutive Constraints in PCB Designs

    Article • ACM Transactions on Design Automation of Electronic Systems, May 2017, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  3. Cell-aware MBFF utilization for clock power reduction

    Article • December 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  4. Single-layer obstacle-aware routing for substrate interconnections

    Article • Integration, September 2015, Elsevier

    Jin-Tai Yan

  5. Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs

    Article • Integration, March 2015, Elsevier

    Jin-Tai Yan

  6. Length-constrained escape routing of differential pairs

    Article • Integration, January 2015, Elsevier

    Jin-Tai Yan

  7. Efficient micro-bump assignment for RDL routing in 3DICs

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  8. Fault-tolerant analysis of TMR design with noise-aware logic

    Article • Integration, September 2014, Elsevier

    Jin-Tai Yan

  9. Feasible region assignment of routing nets in single-layer routing

    Article • June 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  10. Routability-constrained multi-bit flip-flop construction for clock power reduction

    Article • Integration, June 2013, Elsevier

    Jin-Tai Yan

  11. Post-layout redundant wire insertion for fixing min-delay violations

    Article • May 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  12. Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

    Article • January 2013, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  13. Timing-constrained replacement using spare cells for design changes

    Article • January 2013, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  14. Utilization of multi-bit flip-flops for clock power reduction

    Article • December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  15. Direction-constrained layer assignment for rectangle escape routing

    Article • September 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  16. Post-layout OPE-predicted redundant wire insertion for clock skew minimization

    Article • September 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  17. Resource-constrained link insertion for delay reduction

    Article • Integration, September 2012, Elsevier

    Jin-Tai Yan

  18. New optimal layer assignment for bus-oriented escape routing

    Article • Integration, June 2012, Elsevier

    Jin-Tai Yan

  19. Efficient assignment of inter-die signals for die-stacking SiP design

    Article • May 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  20. Density-reduction-oriented layer assignment for rectangle escape routing

    Article • January 2012, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  21. Top-down-based symmetrical buffered clock routing

    Article • January 2012, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  22. IO connection assignment and RDL routing for flip-chip designs

    Article • ACM Transactions on Design Automation of Electronic Systems, October 2011, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  23. Pre-assignment RDL routing via extraction of maximal net sequence

    Article • October 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  24. Simultaneous escape routing based on routability-driven net ordering

    Article • September 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  25. Timing-constrained I/O buffer placement for flip-chip designs

    Article • March 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  26. Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance

    Article • March 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  27. Obstacle-aware length-matching bus routing

    Article • January 2011, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  28. New optimal layer assignment for bus-oriented escape routing

    Article • January 2011, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  29. Routability-driven partitioning-based IO assignment for flip-chip designs

    Article • December 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  30. Routability-driven flip-flop merging process for clock power reduction

    Article • October 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  31. Routability-driven RDL routing with pin reassignment

    Article • September 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  32. Thermal via planning for temperature reduction in 3D ICs

    Article • September 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  33. Construction of constrained multi-bit flip-flops for clock power reduction

    Article • June 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  34. Width-constrained wire sizing for non-tree interconnections

    Article • May 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  35. Low-cost low-power bypassing-based multiplier design

    Article • May 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  36. Ordered escape routing via routability-driven pin assignment

    Article • January 2010, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  37. Two-sided single-detour untangling for bus routing

    Article • January 2010, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  38. Obstacle-aware longest path using rectangular pattern detouring in routing grids

    Article • January 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  39. Resource-constrained timing-driven link insertion for critical delay reduction

    Article • January 2010, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  40. Optimal transformation of non-tree topologies for timing analysis

    Article • November 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  41. Low-power multiplier design with row and column bypassing

    Article • September 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  42. Accurate transformation-based timing analysis for RC non-tree circuits

    Article • May 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  43. Redundant wire insertion for yield improvement

    Article • January 2009, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  44. RDL pre-assignment routing for flip-chip designs

    Article • January 2009, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  45. IO connection assignment and RDL routing for flip-chip designs

    Article • January 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  46. Timing-driven multi-layer Steiner tree construction with obstacle avoidance

    Article • November 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  47. Electromigration-aware rectilinear Steiner tree construction for analog circuits

    Article • November 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  48. Timing-constrained yield-driven redundant via insertion

    Article • November 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  49. Block-level thermal model for floorplan stage in VLSI design flow

    Article • September 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  50. Thermal-driven white space redistribution for block-level floorplans

    Article • August 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  51. Flexible escape routing for flip-chip designs

    Article • August 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  52. Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids

    Article • August 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  53. Packing-driven sliceable transformation for 3D floorplan designs

    Article • June 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  54. Timing-driven Steiner tree construction for three-dimensional ICs

    Article • June 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  55. Noise-aware multiple-voltage assignment for gate-level power optimization

    Article • June 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  56. Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction

    Article • ACM Transactions on Design Automation of Electronic Systems, April 2008, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  57. Routability-Driven Track Routing for Coupling Capacitance Reduction

    Article • December 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  58. Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance

    Article • December 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  59. Top-down-based timing-driven steiner tree construction with wire sizing and buffer insertion

    Article • October 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  60. Timing-constrained redundant via insertion for yield optimization

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  61. Feasible assignment of wire-bonding power pads in hierarchical power quad-grids for signal integrity

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  62. Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity

    Article • May 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  63. Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity

    Article • January 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  64. Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization

    Article • January 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  65. Width and Timing-Constrained Wire Sizing for Critical Area Minimization

    Article • December 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  66. Optimal Network Analysis in Hierarchical Power Quad-Grids

    Article • December 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  67. Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis

    Article • December 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  68. Area-Driven White Space Distribution for Detailed Floorplan Design

    Article • December 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  69. OPC-Aware Routing Reconstruction for OPE Reduction

    Article • August 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  70. Dynamic tree reconstruction with application to timing-constrained congestion-driven global routing

    Article • January 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  71. LB-packing-based floorplan design on DBL representation

    Article • December 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  72. Floorplan-aware Steiner tree reconstruction for optimal buffer insertion

    Article • December 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  73. Timing-driven Steiner tree construction with buffer insertion

    Article • January 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  74. Sliceable transformation of nonslicing floorplans based on vacant block insertion in LB-packing process

    Article • January 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  75. Three-layer bubble-sorting-based nonManhattan channel routing

    Article • ACM Transactions on Design Automation of Electronic Systems, July 2000, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  76. Routability Crossing Distribution and Floating Pin Assignment for T-type Junction Region

    Article • VLSI Design, January 1999, Hindawi Publishing Corporation

    Jin-Tai Yan

  77. An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement

    Article • VLSI Design, January 1999, Hindawi Publishing Corporation

    Jin-Tai Yan

  78. ROUTING SPACE ESTIMATION AND ASSIGNMENT FOR MACRO-CELL PLACEMENT

    Article • Journal of Circuits System and Computers, August 1998, World Scientific Pub Co Pte Lt

    Jin-Tai Yan

  79. An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment

    Article • VLSI Design, January 1996, Hindawi Publishing Corporation

    Jin-Tai Yan

  80. Fuzzy-clustering-based algorithm for circuit partitioning in standard cell placement

    Article • Electronics Letters, February 1995, the Institution of Engineering and Technology (the IET)

    Jin-Tai Yan

  81. Region definition and ordering assignment with the minimization of the number of switchboxes

    Article • January 1995, ACM (Association for Computing Machinery)

    Jin-Tai Yan

  82. A fuzzy clustering algorithm for graph bisection

    Article • Information Processing Letters, December 1994, Elsevier

    Jin-Tai Yan

  83. Genetic-based rotation assignment in macro cell layout

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  84. Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  85. Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  86. Optimal shielding insertion for inductive noise avoidance

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  87. An optimal ILP formulation for minimizing the number of feedthrough cells in standard cell placement

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  88. Area-ratio-constrained min-cut partitioning for row-based placement

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  89. Region definition for minimizing the number of switchboxes and ordering assignment

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  90. Routability crossing distribution and floating terminal assignment of T-type junction region

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  91. Liming-constrained congestion-driven global routing

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  92. Floorplan-aware decoupling capacitance budgeting on equivalent circuit model

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  93. A simple yet effective genetic approach for the orientation assignment on cell-based layout

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  94. A general switchbox router with via minimization

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  95. Printed circuit board routing and package layout codesign

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  96. A new fuzzy-clustering-based approach for two-way circuit partitioning

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  97. An efficient heuristic approach on minimizing the number of feedthrough cells in standard cell placement

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  98. Routing space estimation and safe assignment for macro cell placement

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  99. Region definition and ordering assignment with the minimization of the number of switchboxes

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  100. Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  101. Timing-constrained yield-driven wire sizing for critical area minimization

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  102. Efficient algorithms for two and three-layer over-the-cell channel routing

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  103. A partitioning-based approach for the orientation and rotation assignments of macro cells

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  104. A simulated-annealing-based approach for timing-constrained flexibility-driven routing tree construction

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  105. Multilevel timing-constrained full-chip routing in hierarchical quad-grid model

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  106. Simultaneous wiring and buffer block planning with optimal wire-sizing for interconnect-driven floorplanning

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  107. Orientation assignment of standard cells using a fuzzy mathematical transformation

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  108. The module orientation problem based on Manhattan wire measure is still NP-complete [VLSI design]

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  109. An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  110. Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan

  111. Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Jin-Tai Yan