All Stories

  1. Aging monitor reuse for small delay fault testing
  2. Special session on early life failures
  3. A Neural-Network-Based Fault Classifier
  4. Functional Diagnosis for Graceful Degradation of NoC Switches
  5. Test Strategies for Reconfigurable Scan Networks
  6. High-Throughput Transistor-Level Fault Simulation on GPUs
  7. ETS 2015 best paper
  8. Formal verification of secure reconfigurable scan network infrastructure
  9. Fault tolerance of approximate compute algorithms
  10. Dependable on-chip infrastructure for dependable MPSOCs
  11. Multi-Layer Test and Diagnosis for Dependable NoCs
  12. Efficient observation point selection for aging monitoring
  13. High-Throughput Logic Timing Simulation on GPGPUs
  14. Testing visions
  15. Adaptive multi-layer techniques for increased system dependability
  16. GPU-Accelerated Small Delay Fault Simulation
  17. High Quality System Level Test and Diagnosis
  18. Area-efficient synthesis of fault-secure NoC switches
  19. Test und Diagnose
  20. Incremental computation of delay fault detection probability for variation-aware test generation
  21. Diagnosis of multiple faults with highly compacted test responses
  22. Structural Software-Based Self-Test of Network-on-Chip
  23. SAT-based ATPG beyond stuck-at fault testing
  24. Bit-Flipping Scan - A unified architecture for fault tolerance and offline test
  25. Bit-Flipping Scan - A unified architecture for fault tolerance and offline test
  26. Securing Access to Reconfigurable Scan Networks
  27. Accurate Multi-cycle ATPG in Presence of X-Values
  28. Efficacy and efficiency of algorithm-based fault-tolerance on GPUs
  29. Scan pattern retargeting and merging with reduced access time
  30. Efficient Variation-Aware Statistical Dynamic Timing Analysis for Delay Test Applications
  31. Modeling, verification and pattern generation for reconfigurable scan networks
  32. Scan Test Power Simulation on GPGPUs
  33. Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures
  34. Efficient system-level aging prediction
  35. Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test
  36. Exact stuck-at fault classification in presence of unknowns
  37. Embedded Test for Highly Accurate Defect Localization
  38. Diagnostic Test of Robust Circuits
  39. Efficient BDD-based Fault Simulation in Presence of Unknown Values
  40. P-PET: Partial pseudo-exhaustive test for high defect coverage
  41. Fail-safety in core-based system design
  42. Soft error correction in embedded storage elements
  43. Structural Test for Graceful Degradation of NoC Switches
  44. Structural In-Field Diagnosis for Random Logic Circuits
  45. Towards Variation-Aware Test Methods
  46. On Determining the Real Output Xs by SAT-Based Reasoning
  47. Variation-Aware Fault Modeling
  48. Algorithm-based fault tolerance for many-core architectures
  49. Low-power test planning for arbitrary at-speed delay-test clock schemes
  50. BISD: Scan-based Built-In self-diagnosis
  51. Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen
  52. Generalized Fault Modeling for Logic Diagnosis
  53. Models for Power-Aware Testing
  54. Software-Based Hardware Fault Tolerance for Many-Core Architectures
  55. Power-Aware Design-for-Test
  56. Restrict Encoding for Mixed-Mode BIST
  57. Test Encoding for Extreme Response Compaction
  58. Adaptive Debug and Diagnosis without Fault Dictionaries
  59. Selective Hardening in Early Design Steps
  60. Signature Rollback - A Technique for Testing Robust Circuits
  61. Scan Chain Organization for Embedded Diagnosis
  62. Scan chain organization for embedded diagnosis
  63. Adaptive Debug and Diagnosis without Fault Dictionaries
  64. Programmable deterministic Built-In Self-Test
  65. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor
  66. Test and Testable Design
  67. BIST for systems-on-a-chip
  68. Mixed-Mode BIST Using Embedded Processors
  69. Prüfpfad-Techniken
  70. Einleitung
  71. Hochintegrierte Schaltungen: Prüfgerechter Entwurf und Test
  72. Schaltungs- und Fehlermodellierung
  73. Selbsttestbare Schaltungen
  74. Teststrategien für Schaltwerke
  75. Fehlersimulation
  76. Technologische Grundlagen
  77. Deterministische Testerzeugung für Schaltnetze
  78. Der pseudo-erschöpfende Test
  79. Der Test mit Zufallsmustern
  80. Testverfahren für spezielle Strukturen
  81. Emulation of Scan Paths in Sequential Circuit Synthesis
  82. Automatisierung des Entwurfs vollständig testbarer Schaltungen
  83. Praktische Ergebnisse
  84. Einleitung
  85. Grundlagen. Definitionen und Vorarbeiten
  86. Anwendungen bei Test- und Synthese-Algorithmen
  87. Das Testproblem für integrierte Schaltungen
  88. Die Bestimmung effizienter Zufallstests
  89. Fehlerentdeckungs- und Signalwahrscheinlichkeiten
  90. On fault modeling for dynamic MOS circuits
  91. PROTEST
  92. Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen