All Stories

  1. An Analytical and Empirical Investigation of Tag Partitioning for Energy-Efficient Reliable Cache
  2. An Empirical Fault Vulnerability Exploration of ReRAM-Based Process-in-Memory CNN Accelerators
  3. Improving energy efficiency and fault tolerance of mission-critical cloud task scheduling: A mixed-integer linear programming approach
  4. Interrupt Caching: A Hardware-Assisted Interrupt Handling to Enhance System Responsiveness
  5. Reliability and power consumption models of embedded systems with a machine learning-based optimization
  6. A Low-Cost Fault-Tolerant Racetrack Cache Based on Data Compression
  7. An Energy Efficient Multi-Retention STT-MRAM Memory Architecture for IoT Applications
  8. Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes
  9. A fault-tolerant resource locking protocol for multiprocessor real-time systems
  10. An adaptive data coding scheme for energy consumption reduction in SDN-based Internet of Things
  11. GraphA: An efficient ReRAM-based architecture to accelerate large scale graph processing
  12. CRP: Conditional Replacement Policy for Reliability Enhancement of STT-MRAM Caches
  13. An Architectural-Level Reliability Improvement Scheme in STT-MRAM Main Memory
  14. Data block manipulation for error rate reduction in STT-MRAM based main memory
  15. LETHOR: a thermal-aware proactive routing algorithm for 3D NoCs with less entrance to hot regions
  16. A link adaptation scheme for reliable downlink communications in narrowband IoT
  17. ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories
  18. 3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison
  19. TAMER: an adaptive task allocation method for aging reduction in multi-core embedded real-time systems
  20. CLEAR: Cache Lines Error Accumulation Reduction by exploiting invisible accesses
  21. RAW-Tag: Replicating in Altered Cache Ways for Correcting Multiple-Bit Errors in Tag Array
  22. A-CACHE: Alternating Cache Allocation to Conduct Higher Endurance in NVM-Based Caches
  23. High performance and predictable memory controller for multicore mixed-criticality real-time systems
  24. REACT: Read/Write Error Rate Aware Coding Technique for Emerging STT-MRAM Caches
  25. Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation
  26. TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches
  27. Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits
  28. ROBIN
  29. A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches
  30. WiP: Floating XY-YX: An Efficient Thermal Management Routing Algorithm for 3D NoCs
  31. PCM-oriented cache management strategies for solid-state disks
  32. ORIENT: Organized interleaved ECCs for new STT-MRAM caches
  33. SMARTag: Error Correction in Cache Tag Array by Exploiting Address Locality
  34. RI-COTS: Trading performance for reliability improvements in commercial of the shelf systems
  35. Investigating the effects of process variations and system workloads on endurance of non-volatile caches
  36. OPTIMAS: Overwrite Purging Through In-Execution Memory Address Snooping to Improve Lifetime of NVM-Based Scratchpad Memories
  37. AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches
  38. WIPE: Wearout Informed Pattern Elimination to Improve the Endurance of NVM-based Caches
  39. A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction
  40. Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches
  41. An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors
  42. A2CM2: aging-aware cache memory management technique
  43. A partial task replication algorithm for fault- tolerant FPGA-based soft-multiprocessors
  44. In-scratchpad memory replication: Protecting scratchpad memories in multicores against soft errors
  45. LATED: Lifetime-Aware Tag for Enduring Design
  46. A data recomputation approach for reliability improvement of scratchpad memory in embedded systems
  47. PSP-Cache: A low-cost fault-tolerant cache memory architecture
  48. PSP-Cache: A low-cost fault-tolerant cache memory architecture
  49. FTSPM: A Fault-Tolerant ScratchPad Memory
  50. Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors
  51. Low Cost Concurrent Error Detection for On-Chip Memory Based Embedded Processors