All Stories

  1. A 0.5 to 1.7 Gbps PI-CDR with a Wide Frequency-Tracking Range
  2. A Self-adaptation Method of Fitting Convolutional Neural Network into FPGA
  3. A closed-loop interface for capacitive micro-accelerometers with pulse-width-modulation force feedback
  4. NAND-NOR
  5. FPGA High-level Synthesis versus Overlay
  6. Harmonic-free and low cost delay-locked loop
  7. high speed interface
  8. Low Cost 1D DCT Core for Multiple Video Codec
  9. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications
  10. A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability
  11. Efficiently Exploring FPGA Design Space Based on Semi-Supervised Learning
  12. On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time
  13. A smart sensory platform based on field programmable analog array
  14. A Multiphase DLL With a Novel Fast-Locking Fine-Code Time-to-Digital Converter
  15. A low power 12-bit 1 Msps successive approximation register ADC with an improved switching procedure
  16. Analysis of parasitic feed-through capacitance effect in closed-loop drive circuit design for capacitive micro-gyroscope
  17. A 1.3μW 0.7μVRMS chopper current-reuse instrumentation amplifier for EEG applications
  18. A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler
  19. Size aware placement for island style FPGAs
  20. A highly-integrated wireless configuration circuit for FPGA chip
  21. A CMOS Triple Inter-Locked Latch for SEU Insensitivity Design
  22. Architecture model and resource graph building algorithm for detailed FPGA architecture design
  23. A multi-mode interface for MEMS vibratory gyroscope with self-tuned filter
  24. A programmable wireless platform for biomedical signal acquisition
  25. Design and analysis of a dual mode CMOS field programmable analog array
  26. Review of advanced FPGA architectures and technologies
  27. Exploring architecture parameters for dual-output LUT based FPGAs
  28. A −115dB PSRR CMOS bandgap reference with a novel voltage self-regulating technique
  29. A semi-supervised modeling approach for performance characterization of FPGA architectures
  30. A survey of open source processors for FPGAs
  31. Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method
  32. A multimode DLL with trade-off between multiphase and static phase error
  33. A programmable analog hearing aid system-on-chip with frequency compensation
  34. Successive approximation time-to-digital converter based on vernier charging method
  35. Revisiting and-inverter cones
  36. Air-gap-based RF coaxial TSV and its characteristic analysis
  37. A 97 dB dynamic range CSA-based readout circuit with analog temperature compensation for MEMS capacitive sensors
  38. Analysis and Design of a 3rd Order Velocity-Controlled Closed-Loop for MEMS Vibratory Gyroscopes
  39. A fast-locking digital DLL with a high resolution time-to-digital converter
  40. A CMOS Field Programmable Analog Array for intelligent sensory application
  41. Timing-constrained minimum area/power FPGA memory mapping
  42. A dual-band quadrature VCO with gain proportional to oscillation frequency
  43. A baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness
  44. A fully integrated 3.5 GHz CMOS differential power amplifier driver
  45. A wide load range, multi-mode synchronous buck DC—DC converter with a dynamic mode controller and adaptive slope compensation
  46. A 2.1 μA wake-up circuit for Chinese ETC system
  47. A feed-forward AGC circuit with 48 dB-gain range, 1.2 μs minimum settling time for WiMAX receiver
  48. High-Performance Closed-Loop Interface Circuit for High-Q Capacitive Microaccelerometers
  49. A Range-Extended and Area-Efficient Time-to-Digital Converter Utilizing Ring-Tapped Delay Line
  50. A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation
  51. RF-TSV design, modeling and application for 3D multi-core computer systems
  52. A fast foreground digital calibration technique for pipelined ADC
  53. A 12-bit, 40-Ms/s pipelined ADC with an improved operational amplifier
  54. Dual-mode gain control for a 1 V CMOS hearing aid device with enhanced accuracy and energy-efficiency
  55. Performance evaluation of air-gap-based coaxial RF TSV for 3D NoC
  56. Self-test method and recovery mechanism for high frequency TSV array
  57. A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA
  58. A Vernier Delay Line for Time Interval Measurement
  59. A pseudo differentialGm—Ccomplex filter with frequency tuning for IEEE802.15.4 applications
  60. A current mode feed-forward gain control system for a 0.8 V CMOS hearing aid
  61. Current Mode Feed-Forward Gain Control for 0.8V CMOS hearing aid
  62. A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA
  63. Direct model extraction of RFCMOS spiral transformers
  64. Electrical characterization of RF TSV for 3D multi-core and heterogeneous ICs
  65. A multimode, power-adjustable transmitter for UHF mobile RFID reader
  66. Overview: Emerging technologies on giga-scale FPGA implementat
  67. MOP-DDPG: Multiple Observation Points Oriented Deterministic Diagnostic Pattern Generation for Compound Faults
  68. Noise and mismatch optimization for capacitive MEMS readout
  69. An area-saving dual-path loop filter for low-voltage integrated phase-locked loops
  70. FPGA based on integration of carbon nanorelays and CMOS devices
  71. A high precision CMOS weak current readout circuit
  72. A simple method of measuring differentially-excited on-wafer spiral inductor-like components
  73. A Reliability Circuit Implementation for VLSI with Combined Huffman and CRC Coding
  74. A large dynamic range CMOS readout circuit for MEMS vibratory gyroscope
  75. A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range
  76. A low-noise readout circuit for MEMS vibratory gyroscope
  77. CMOS digitalized peak detector for a MEMS-based electrostatic field sensor
  78. Asymmetrical parasitic effects in differential inductor
  79. Efficient CMOS Preamplifier Dedicated for a MEMS-Based Electrostatic Field Sensor
  80. Use of VPR in Design of FPGA Architecture
  81. Design, measurement and analysis of CMOS polysilicon TFT operational amplifiers
  82. Circuit performance of low temperature CMOS polysilicon TFT operational amplifiers
  83. Fabrication and Performance of Digital and Analogue Poly-Si TFT Circuits on Glass
  84. Statistical model for evaluation of effects of nonuniformity in optically-programmed neural networks
  85. Switch-level timing verification for CMOS circuits: a semianalytic approach
  86. A Fully CMOS-integrated pH-ISFET Interface Circuit
  87. A semi-analytic slope delay model for CMOS switch-level timing verification
  88. A hierarchical approach to timing verification in CMOS VLSI design