All Stories

  1. Beyond RSS: Towards Intelligent Dynamic Memory Management (Work in Progress)
  2. A Framework for the Protection of Critical Infrastructures from Combined Cyber and Physical Threats
  3. The Unexpected Efficiency of Bin Packing Algorithms for Dynamic Storage Allocation in the Wild: An Intellectual Abstract
  4. A Methodology for enhancing Emergency Situational Awareness through Social Media
  5. Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey
  6. FADE
  7. Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs
  8. Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers
  9. FPGA Acceleration of Short Read Alignment
  10. Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC
  11. EVOLVE
  12. Scale-out beam longitudinal dynamics simulations
  13. A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications
  14. Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers
  15. Oops
  16. Energy-Efficient VLSI Implementation of Multipliers with Double LSB Operands
  17. Single- and Multi-FPGA Acceleration of Dense Stereo Vision for Planetary Rovers
  18. PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs
  19. OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures
  20. Distributed Trade-Based Edge Device Management in Multi-Gateway IoT
  21. A Hierarchical Distributed Runtime Resource Management Scheme for NoC-Based Many-Cores
  22. High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation
  23. Runtime Slack Creation for Processor Performance Variability using System Scenarios
  24. SoftRM
  25. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations
  26. AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics
  27. Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space
  28. FabSpace 2.0: A platform for application and service development based on Earth Observation data
  29. Spark acceleration on FPGAs: A use case on machine learning in Pynq
  30. An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC
  31. Application performance improvement by exploiting process variability on FPGA devices
  32. A low-complexity control mechanism targeting smart thermostats
  33. HARPA: Tackling physically induced performance variability
  34. A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis
  35. Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference
  36. Parameter Sensitivity in Virtual FPGA Architectures
  37. CF-TUNE: Collaborative Filtering Auto-Tuning for Energy Efficient Many-core Processors
  38. Dataflow Acceleration of scikit-learn Gaussian Process Regression
  39. Optimizing Extended Hodgkin-Huxley Neuron Model Simulations for a Xeon/Xeon Phi Node
  40. Agora: Agent and market-based resource management for many-core systems
  41. Computation offloading and resource allocation for low-power IoT edge devices
  42. A 56 Gbaud reconfigurable FPGA feed-forward equalizer for optical datacenter networks with flexible baudrate- and modulation-format
  43. A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s
  44. A Customizable Framework for Application Implementation onto 3-D FPGAs
  45. Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
  46. Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory
  47. A survey on reconfigurable accelerators for cloud computing
  48. HW/SW Codesign and FPGA Acceleration of Visual Odometry Algorithms for Rover Navigation on Mars
  49. An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems
  50. A Systematic Methodology for Optimization of Applications Utilizing Concurrent Data Structures
  51. A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures
  52. Performance and energy evaluation of spark applications on low-power SoCs
  53. An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures
  54. Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend
  55. Near-Static Shading Exploration for Smart Photovoltaic Module Topologies Based on Snake-like Configurations
  56. Accuracy of Quasi-Monte Carlo technique in failure probability estimations
  57. ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization
  58. First impressions from detailed brain model simulations on a Xeon/Xeon-Phi node
  59. Parallel application placement onto 3-D reconfigurable architectures
  60. ECG signal analysis and arrhythmia detection on IoT wearable medical devices
  61. Customization methodology for implementation of streaming aggregation in embedded systems
  62. Performance analysis of accelerated biophysically-meaningful neuron simulations
  63. Efficient variability analysis of arithmetic units using linear regression techniques
  64. Runtime Interval Optimization and Dependable Performance for Application-Level Checkpointing
  65. Runtime management of adaptive MPSoCs for graceful degradation
  66. Capturing True Workload Dependency of BTI-induced Degradation in CPU Components
  67. A Survey on FEC Codes for 100 G and Beyond Optical Networks
  68. A Co-Design Approach For Rapid Prototyping Of Image Processing On SoC FPGAs
  69. The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres
  70. Deploying and monitoring hadoop MapReduce analytics on single-chip cloud computer
  71. Distributed QoS management for internet of things under resource constraints
  72. An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs
  73. A MapReduce scratchpad memory for multi-core cloud computing applications
  74. Advancing Integrated and Personalized Healthcare Services, the AEGLE Approach
  75. Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform
  76. Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems
  77. High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs
  78. Preface
  79. Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS
  80. Platform-aware dynamic data type refinement methodology for radix tree Data Structures
  81. Many-core CPUs can deliver scalable performance to stochastic simulations of large-scale biochemical reaction networks
  82. Hybrid approximate multiplier architectures for improved power-accuracy trade-offs
  83. Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures
  84. HARPA: Solutions for dependable performance under physically induced performance variability
  85. AEGLE: A big bio-data analytics framework for integrated health-care services
  86. Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models
  87. Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations
  88. Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane
  89. Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems
  90. GENESIS
  91. SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms
  92. Trusted Computing for Embedded Systems
  93. Applied Reconfigurable Computing
  94. Dynamic Memory Management for Embedded Systems
  95. Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach
  96. Using Chaos Theory based workload analysis to perform Dynamic Frequency Scaling on MPSoCs
  97. An Energy Efficient Message Passing Synchronization Algorithm for Concurrent Data Structures in Embedded Systems
  98. SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring
  99. A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware
  100. TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools
  101. Effective Learning and Filtering of Faulty Heart-Beats for Advanced ECG Arrhythmia Detection using MIT-BIH Database
  102. Plug&Chip
  103. A Framework for Supporting Adaptive Fault-Tolerant Solutions
  104. Linear regression techniques for efficient analysis of transistor variability
  105. A MapReduce framework implementation for Network-on-Chip platforms
  106. Heap Management for Trusted Operating Environments
  107. Reconfigurable FEC codes for software-defined optical transceivers
  108. A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs
  109. Introduction
  110. Intermediate Variable Removal from Dynamic Applications
  111. Systematic Placement of Dynamic Objects Across Heterogeneous Memory Hierarchies
  112. Dynamic Data Types Optimization in Multimedia and Communication Applications
  113. Analysis and Characterization of Dynamic Multimedia Applications
  114. Profiling and Analysis of Dynamic Applications
  115. Dynamic Memory Management Optimization for Multimedia Applications
  116. Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems
  117. Performance and power consumption evaluation of concurrent queue implementations in embedded systems
  118. Evaluation of message passing synchronization algorithms in embedded systems
  119. Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud Computer
  120. A framework for rapid evaluation of heterogeneous 3-D NoC architectures
  121. Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations
  122. A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms
  123. A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time
  124. A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders
  125. The Enexal Bauxite Residue Treatment Process: Industrial Scale Pilot Plant Results
  126. Designing 2D and 3D Network-on-Chip Architectures
  127. A novel 3-D FPGA architecture targeting communication intensive applications
  128. Hardware Accelerated Rician Denoise Algorithm for High Performance Magnetic Resonance Imaging
  129. A HW/SW Framework Emulating Wearable Devices For Remote Wound Monitoring and Management
  130. Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks
  131. Power-aware dynamic memory management on many-core platforms utilizing DVFS
  132. A low-cost fault tolerant solution targeting commercial FPGA devices
  133. SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots
  134. The SYSMANTIC NoC Design and Prototyping Framework
  135. NoC-Based System Integration
  136. Projects on Network-on-Chip
  137. NoC Verification and Testing
  138. Communication Architecture
  139. Middleware Memory Management in NoC
  140. Power and Thermal Effects and Management
  141. NoC Modeling and Topology Exploration
  142. The Spidergon STNoC
  143. On Designing 3-D Platforms
  144. Network-on-Chip Technology: A Paradigm Shift
  145. A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization
  146. A low-complexity implementation of QC-LDPC encoder in reconfigurable logic
  147. Automatic implementation of low-complexity QC-LDPC encoders
  148. Automatic implementation of low-complexity QC-LDPC encoders
  149. System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework
  150. A Process-based Reconfigurable SystemC Module for simulation speedup
  151. JITPR
  152. SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy
  153. Arterial Dissection
  154. On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs
  155. HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips
  156. Hypervised Transient SPICE Simulations of Large Netlists & Workloads on Multi-Processor Systems
  157. Performance Evaluation of Embedded Processor in MapReduce Cloud Computing Applications
  158. Distributed run-time resource management for malleable applications on many-core platforms
  159. Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation
  160. Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
  161. High-level customization framework for application-specific NoC architectures
  162. Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios
  163. Adaptive dynamic memory allocators by estimating application workloads
  164. Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments
  165. A low-cost fault tolerant solution targeting to commercial FPGA devices
  166. On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation
  167. A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
  168. Scalable Multi-core Architectures
  169. A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems
  170. Framework for performing rapid evaluation of 3D SoCs
  171. Design and experimentation with low-power morphable multipliers
  172. Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm
  173. Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow
  174. Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios
  175. Application-Specific Multi-Threaded Dynamic Memory Management
  176. A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs
  177. A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
  178. Thermal optimization for micro-architectures through selective block replication
  179. Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations
  180. FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer
  181. CAD tools for designing 3D integrated systems
  182. Keynote speech 2: Reconfigurable systems and 3D architectures
  183. A reconfigurable IP characterization technique improving high-level synthesis results
  184. A novel methodology for architecture-level exploration of 3D SoCs
  185. A standard-cell library suite for deep-deep sub-micron CMOS technologies
  186. High Performance and Area Efficient Flexible DSP Datapath Synthesis
  187. On Supporting Rapid Thermal Analysis
  188. Three Dimensional System Integration
  189. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning
  190. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
  191. The MOSART Mapping Optimization for Multi-Core ARchiTectures
  192. A Framework for Architecture-Level Exploration of 3-D FPGA Platforms
  193. A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework
  194. Multiple Vdd on 3D NoC architectures
  195. A Methodology for Alleviating the Performance Degradation of TMR Solutions
  196. BIT-width exploration over 3D architectures using high-level synthesis
  197. Introduction to Three-Dimensional Integration
  198. Towards Supporting Fault-Tolerance in FPGAs
  199. A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd
  200. High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures
  201. Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures
  202. Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching
  203. Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms
  204. Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach
  205. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
  206. Software metadata: Systematic characterization of the memory behaviour of dynamic applications
  207. Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology
  208. A NOVEL ALLOCATION METHODOLOGY FOR PARTIAL AND DYNAMIC BITSTREAM GENERATION FOR FPGA ARCHITECTURES
  209. Construction of dual mode components for reconfiguration aware high-level synthesis
  210. VLSI-SoC: Design Methodologies for SoC and SiP
  211. Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems
  212. A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
  213. A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  214. A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
  215. Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms
  216. MNEMEE
  217. Dynamic Data Type Optimization and Memory Assignment Methodologies
  218. Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip
  219. Compilation Technique for Loop Overhead Minimization
  220. Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations
  221. Node resource management for DSP applications on 3D Network-on-Chip architecture
  222. Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems
  223. A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
  224. Three-Dimensional Networks-on-Chip Architectures
  225. An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
  226. A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  227. Aortic Function in Beta-Thalassemia Major
  228. Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms
  229. Designing a novel high-performance FPGA architecture for data intensive applications
  230. Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility
  231. Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays
  232. Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information
  233. Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology
  234. A software-supported methodology for designing high-performance 3D FPGA architectures
  235. Implementing cellular automata modeled applications on network-on-chip platforms
  236. Systematic methodology for exploration of performance – Energy trade-offs in network applications using Dynamic Data Type refinement
  237. Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns
  238. Preface of Special Issue on VLSI Design and Test
  239. Preface
  240. Fine- and Coarse-Grain Reconfigurable Computing
  241. A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs
  242. Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation
  243. Application - specific NoC platform design based on System Level Optimization
  244. Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique
  245. An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems
  246. Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance
  247. Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors
  248. Systematic dynamic memory management design methodology for reduced memory footprint
  249. Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
  250. Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures
  251. Energy-efficient dynamic memory allocators at the middleware level of embedded systems
  252. A novel methodology for designing high-performance and low-energy FPGA routing architecture
  253. Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources
  254. Circuits Techniques for Dynamic Power Reduction
  255. A method for partitioning applications in hybrid reconfigurable architectures
  256. Editorial: Power and timing modelling, optimisation and simulation
  257. Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications
  258. Improving the Memory Bandwidth Utilization Using Loop Transformations
  259. International EMS systems: Greece
  260. Circuits Techniques for Dynamic Power Reduction
  261. A Novel Data-Path for Accelerating DSP Kernels
  262. Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology
  263. Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications
  264. Designing CMOS Circuits for Low Power
  265. Motivation, Context and Objectives
  266. Logic Level Power Optimization
  267. Sources of Power Dissipation in CMOS Circuits
  268. THE DESIGN OF A RIPPLE CARRY ADIABATIC ADDER
  269. Integrated Circuit Design
  270. Run-Time Power Management for Low and Medium Bit-Rate Digital Receivers
  271. Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations
  272. Ateleological Developments of "Design-Decisions-Independent" Information Systems
  273. Designing Heterogeneous FPGAs with Multiple SBs
  274. System-Level Application-Specific NoC Design for Network and Multimedia Applications
  275. Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption
  276. Systematic design of novel architectures for implementation of Radon Transform
  277. Designing efficient redundant arithmetic processors for DSP applications
  278. Design methodology for direct mapping of iterative algorithms on array architectures
  279. Design methodology of mapping iterative algorithms on piecewise regular processor arrays
  280. Methodology for the design of signed-digit DSP processors
  281. A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
  282. A window-based color quantization technique and its embedded implementation
  283. A novel division algorithm for parallel and sequential processing
  284. Methodology for the design of signed-digit DSP processors
  285. A systematic methodology for designing multilevel systolic architectures
  286. Abstract and Concrete Data Type Optimizations at the UML and C/C++ Level for Dynamic Embedded Software
  287. Data and instruction memory performance and energy optimization technique
  288. A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools
  289. A Survey of Existing Fine-Grain Reconfigurable Architectures and CAD tools
  290. A low-energy FPGA: architecture design and software-supported design flow
  291. A Methodology for Partitioning DSP Applications in Hybrid Reconfigurable Systems
  292. A Petri net approach to the design of processor array architectures
  293. A systematic methodology for designing multilevel systolic architectures
  294. Low-power design of array architectures