All Stories

  1. Making Peer-to-Peer Federated Learning Work Smoothly Across Different Devices
  2. Leveraging DVFS for Energy-Efficient and QoS-aware Edge Video Analytics
  3. Approximate Computing Survey, Part II: Application-Specific & Architectural Approximation Techniques and Applications
  4. Approximate Computing Survey, Part I: Terminology and Software & Hardware Approximation Techniques
  5. CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design Optimization
  6. Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations
  7. Data-driven HLS optimization for reconfigurable accelerators
  8. Late Breaking Results: Language-level QoR modeling for High-Level Synthesis
  9. Seamless HW-accelerated AI serving in heterogeneous MEC Systems with AI@EDGE
  10. Beyond RSS: Towards Intelligent Dynamic Memory Management (Work in Progress)
  11. A Framework for the Protection of Critical Infrastructures from Combined Cyber and Physical Threats
  12. The Unexpected Efficiency of Bin Packing Algorithms for Dynamic Storage Allocation in the Wild: An Intellectual Abstract
  13. A Methodology for enhancing Emergency Situational Awareness through Social Media
  14. Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey
  15. FADE
  16. Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs
  17. Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers
  18. FPGA Acceleration of Short Read Alignment
  19. Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC
  20. EVOLVE
  21. Scale-out beam longitudinal dynamics simulations
  22. A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications
  23. Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers
  24. Energy-Efficient VLSI Implementation of Multipliers with Double LSB Operands
  25. Single- and Multi-FPGA Acceleration of Dense Stereo Vision for Planetary Rovers
  26. Oops
  27. PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs
  28. OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures
  29. Distributed Trade-Based Edge Device Management in Multi-Gateway IoT
  30. A Hierarchical Distributed Runtime Resource Management Scheme for NoC-Based Many-Cores
  31. A Framework Exploiting Process Variability to Improve Energy Efficiency in FPGA Applications
  32. High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation
  33. Runtime Slack Creation for Processor Performance Variability using System Scenarios
  34. SoftRM
  35. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations
  36. AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics
  37. Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space
  38. Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference
  39. FabSpace 2.0: A platform for application and service development based on Earth Observation data
  40. Spark acceleration on FPGAs: A use case on machine learning in Pynq
  41. An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC
  42. Application performance improvement by exploiting process variability on FPGA devices
  43. A low-complexity control mechanism targeting smart thermostats
  44. HARPA: Tackling physically induced performance variability
  45. A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis
  46. Parameter Sensitivity in Virtual FPGA Architectures
  47. CF-TUNE: Collaborative Filtering Auto-Tuning for Energy Efficient Many-core Processors
  48. Dataflow Acceleration of scikit-learn Gaussian Process Regression
  49. Optimizing Extended Hodgkin-Huxley Neuron Model Simulations for a Xeon/Xeon Phi Node
  50. Agora: Agent and market-based resource management for many-core systems
  51. Computation offloading and resource allocation for low-power IoT edge devices
  52. A 56 Gbaud reconfigurable FPGA feed-forward equalizer for optical datacenter networks with flexible baudrate- and modulation-format
  53. A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s
  54. A Customizable Framework for Application Implementation onto 3-D FPGAs
  55. Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
  56. Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory
  57. A survey on reconfigurable accelerators for cloud computing
  58. HW/SW Codesign and FPGA Acceleration of Visual Odometry Algorithms for Rover Navigation on Mars
  59. An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems
  60. A Systematic Methodology for Optimization of Applications Utilizing Concurrent Data Structures
  61. A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures
  62. Performance and energy evaluation of spark applications on low-power SoCs
  63. An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures
  64. Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend
  65. Near-Static Shading Exploration for Smart Photovoltaic Module Topologies Based on Snake-like Configurations
  66. Accuracy of Quasi-Monte Carlo technique in failure probability estimations
  67. ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization
  68. First impressions from detailed brain model simulations on a Xeon/Xeon-Phi node
  69. Parallel application placement onto 3-D reconfigurable architectures
  70. ECG signal analysis and arrhythmia detection on IoT wearable medical devices
  71. Customization methodology for implementation of streaming aggregation in embedded systems
  72. Performance analysis of accelerated biophysically-meaningful neuron simulations
  73. Efficient variability analysis of arithmetic units using linear regression techniques
  74. Runtime Interval Optimization and Dependable Performance for Application-Level Checkpointing
  75. Runtime management of adaptive MPSoCs for graceful degradation
  76. Capturing True Workload Dependency of BTI-induced Degradation in CPU Components
  77. A Survey on FEC Codes for 100 G and Beyond Optical Networks
  78. A Co-Design Approach For Rapid Prototyping Of Image Processing On SoC FPGAs
  79. The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres
  80. Deploying and monitoring hadoop MapReduce analytics on single-chip cloud computer
  81. Distributed QoS management for internet of things under resource constraints
  82. An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs
  83. A MapReduce scratchpad memory for multi-core cloud computing applications
  84. Advancing Integrated and Personalized Healthcare Services, the AEGLE Approach
  85. Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform
  86. Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems
  87. High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs
  88. Preface
  89. Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS
  90. Platform-aware dynamic data type refinement methodology for radix tree Data Structures
  91. Many-core CPUs can deliver scalable performance to stochastic simulations of large-scale biochemical reaction networks
  92. Hybrid approximate multiplier architectures for improved power-accuracy trade-offs
  93. Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures
  94. HARPA: Solutions for dependable performance under physically induced performance variability
  95. AEGLE: A big bio-data analytics framework for integrated health-care services
  96. Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models
  97. Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations
  98. Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane
  99. Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems
  100. GENESIS
  101. SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms
  102. Trusted Computing for Embedded Systems
  103. Applied Reconfigurable Computing
  104. Dynamic Memory Management for Embedded Systems
  105. Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach
  106. Using Chaos Theory based workload analysis to perform Dynamic Frequency Scaling on MPSoCs
  107. An Energy Efficient Message Passing Synchronization Algorithm for Concurrent Data Structures in Embedded Systems
  108. SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring
  109. A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware
  110. TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools
  111. Effective Learning and Filtering of Faulty Heart-Beats for Advanced ECG Arrhythmia Detection using MIT-BIH Database
  112. Plug&Chip
  113. A Framework for Supporting Adaptive Fault-Tolerant Solutions
  114. Linear regression techniques for efficient analysis of transistor variability
  115. A MapReduce framework implementation for Network-on-Chip platforms
  116. Heap Management for Trusted Operating Environments
  117. Reconfigurable FEC codes for software-defined optical transceivers
  118. A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs
  119. Introduction
  120. Intermediate Variable Removal from Dynamic Applications
  121. Systematic Placement of Dynamic Objects Across Heterogeneous Memory Hierarchies
  122. Dynamic Data Types Optimization in Multimedia and Communication Applications
  123. Analysis and Characterization of Dynamic Multimedia Applications
  124. Profiling and Analysis of Dynamic Applications
  125. Dynamic Memory Management Optimization for Multimedia Applications
  126. Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems
  127. Performance and power consumption evaluation of concurrent queue implementations in embedded systems
  128. Evaluation of message passing synchronization algorithms in embedded systems
  129. Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud Computer
  130. A framework for rapid evaluation of heterogeneous 3-D NoC architectures
  131. Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations
  132. A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms
  133. A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time
  134. A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders
  135. The Enexal Bauxite Residue Treatment Process: Industrial Scale Pilot Plant Results
  136. Designing 2D and 3D Network-on-Chip Architectures
  137. A novel 3-D FPGA architecture targeting communication intensive applications
  138. Hardware Accelerated Rician Denoise Algorithm for High Performance Magnetic Resonance Imaging
  139. A HW/SW Framework Emulating Wearable Devices For Remote Wound Monitoring and Management
  140. Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks
  141. Power-aware dynamic memory management on many-core platforms utilizing DVFS
  142. A low-cost fault tolerant solution targeting commercial FPGA devices
  143. SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots
  144. The SYSMANTIC NoC Design and Prototyping Framework
  145. NoC-Based System Integration
  146. Projects on Network-on-Chip
  147. NoC Verification and Testing
  148. Communication Architecture
  149. Middleware Memory Management in NoC
  150. Power and Thermal Effects and Management
  151. NoC Modeling and Topology Exploration
  152. The Spidergon STNoC
  153. On Designing 3-D Platforms
  154. Network-on-Chip Technology: A Paradigm Shift
  155. A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization
  156. A low-complexity implementation of QC-LDPC encoder in reconfigurable logic
  157. Automatic implementation of low-complexity QC-LDPC encoders
  158. Automatic implementation of low-complexity QC-LDPC encoders
  159. System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework
  160. A Process-based Reconfigurable SystemC Module for simulation speedup
  161. JITPR
  162. SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy
  163. Arterial Dissection
  164. On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs
  165. HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips
  166. Hypervised Transient SPICE Simulations of Large Netlists & Workloads on Multi-Processor Systems
  167. Performance Evaluation of Embedded Processor in MapReduce Cloud Computing Applications
  168. Distributed run-time resource management for malleable applications on many-core platforms
  169. Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation
  170. Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
  171. High-level customization framework for application-specific NoC architectures
  172. Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios
  173. Adaptive dynamic memory allocators by estimating application workloads
  174. Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments
  175. A low-cost fault tolerant solution targeting to commercial FPGA devices
  176. On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation
  177. A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
  178. Scalable Multi-core Architectures
  179. A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems
  180. Framework for performing rapid evaluation of 3D SoCs
  181. Design and experimentation with low-power morphable multipliers
  182. Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm
  183. Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow
  184. Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios
  185. Application-Specific Multi-Threaded Dynamic Memory Management
  186. A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs
  187. A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
  188. Thermal optimization for micro-architectures through selective block replication
  189. Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations
  190. FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer
  191. CAD tools for designing 3D integrated systems
  192. Keynote speech 2: Reconfigurable systems and 3D architectures
  193. A reconfigurable IP characterization technique improving high-level synthesis results
  194. A novel methodology for architecture-level exploration of 3D SoCs
  195. A standard-cell library suite for deep-deep sub-micron CMOS technologies
  196. High Performance and Area Efficient Flexible DSP Datapath Synthesis
  197. On Supporting Rapid Thermal Analysis
  198. Three Dimensional System Integration
  199. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning
  200. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
  201. The MOSART Mapping Optimization for Multi-Core ARchiTectures
  202. A Framework for Architecture-Level Exploration of 3-D FPGA Platforms
  203. A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework
  204. Multiple Vdd on 3D NoC architectures
  205. A Methodology for Alleviating the Performance Degradation of TMR Solutions
  206. BIT-width exploration over 3D architectures using high-level synthesis
  207. Introduction to Three-Dimensional Integration
  208. Towards Supporting Fault-Tolerance in FPGAs
  209. A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd
  210. High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures
  211. Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures
  212. Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching
  213. Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms
  214. Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach
  215. Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
  216. Software metadata: Systematic characterization of the memory behaviour of dynamic applications
  217. Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology
  218. A NOVEL ALLOCATION METHODOLOGY FOR PARTIAL AND DYNAMIC BITSTREAM GENERATION FOR FPGA ARCHITECTURES
  219. Construction of dual mode components for reconfiguration aware high-level synthesis
  220. VLSI-SoC: Design Methodologies for SoC and SiP
  221. Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems
  222. A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
  223. A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  224. A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
  225. Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms
  226. MNEMEE
  227. Dynamic Data Type Optimization and Memory Assignment Methodologies
  228. Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip
  229. Compilation Technique for Loop Overhead Minimization
  230. Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations
  231. Node resource management for DSP applications on 3D Network-on-Chip architecture
  232. Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems
  233. A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
  234. Three-Dimensional Networks-on-Chip Architectures
  235. An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
  236. A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs
  237. Aortic Function in Beta-Thalassemia Major
  238. Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms
  239. Designing a novel high-performance FPGA architecture for data intensive applications
  240. Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility
  241. Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays
  242. Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information
  243. Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology
  244. A software-supported methodology for designing high-performance 3D FPGA architectures
  245. Implementing cellular automata modeled applications on network-on-chip platforms
  246. Systematic methodology for exploration of performance – Energy trade-offs in network applications using Dynamic Data Type refinement
  247. Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns
  248. Preface of Special Issue on VLSI Design and Test
  249. Preface
  250. Fine- and Coarse-Grain Reconfigurable Computing
  251. A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs
  252. Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation
  253. Application - specific NoC platform design based on System Level Optimization
  254. Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique
  255. An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems
  256. Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance
  257. Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors
  258. Systematic dynamic memory management design methodology for reduced memory footprint
  259. Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
  260. Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures
  261. Energy-efficient dynamic memory allocators at the middleware level of embedded systems
  262. A novel methodology for designing high-performance and low-energy FPGA routing architecture
  263. Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources
  264. Circuits Techniques for Dynamic Power Reduction
  265. A method for partitioning applications in hybrid reconfigurable architectures
  266. Editorial: Power and timing modelling, optimisation and simulation
  267. Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications
  268. Improving the Memory Bandwidth Utilization Using Loop Transformations
  269. International EMS systems: Greece
  270. Circuits Techniques for Dynamic Power Reduction
  271. A Novel Data-Path for Accelerating DSP Kernels
  272. Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology
  273. Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications
  274. Designing CMOS Circuits for Low Power
  275. Motivation, Context and Objectives
  276. Logic Level Power Optimization
  277. Sources of Power Dissipation in CMOS Circuits
  278. THE DESIGN OF A RIPPLE CARRY ADIABATIC ADDER
  279. Integrated Circuit Design
  280. Run-Time Power Management for Low and Medium Bit-Rate Digital Receivers
  281. Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations
  282. Ateleological Developments of "Design-Decisions-Independent" Information Systems
  283. Designing Heterogeneous FPGAs with Multiple SBs
  284. System-Level Application-Specific NoC Design for Network and Multimedia Applications
  285. Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption
  286. Systematic design of novel architectures for implementation of Radon Transform
  287. Designing efficient redundant arithmetic processors for DSP applications
  288. Design methodology for direct mapping of iterative algorithms on array architectures
  289. Design methodology of mapping iterative algorithms on piecewise regular processor arrays
  290. Methodology for the design of signed-digit DSP processors
  291. A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
  292. A window-based color quantization technique and its embedded implementation
  293. A novel division algorithm for parallel and sequential processing
  294. Methodology for the design of signed-digit DSP processors
  295. A systematic methodology for designing multilevel systolic architectures
  296. Abstract and Concrete Data Type Optimizations at the UML and C/C++ Level for Dynamic Embedded Software
  297. Data and instruction memory performance and energy optimization technique
  298. A Survey of Coarse-Grain Reconfigurable Architectures and Cad Tools
  299. A Survey of Existing Fine-Grain Reconfigurable Architectures and CAD tools
  300. A low-energy FPGA: architecture design and software-supported design flow
  301. A Methodology for Partitioning DSP Applications in Hybrid Reconfigurable Systems
  302. A Petri net approach to the design of processor array architectures
  303. A systematic methodology for designing multilevel systolic architectures
  304. Low-power design of array architectures