All Stories

  1. Post-Model Validation of Victim DRAM Caches

    Article • November 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Debiprasanna Sahoo

  2. Formal Modeling and Verification of NAND Flash Memory Supporting Advanced Operations

    Article • November 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Debiprasanna Sahoo

  3. Formal Modeling and Verification of a Victim DRAM Cache

    Article • ACM Transactions on Design Automation of Electronic Systems, March 2019, ACM (Association for Computing Machinery)

    Madhu Mutyam, Dr Debiprasanna Sahoo

  4. Multidimensional Grid Aware Address Prediction for GPGPU

    Article • January 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Debiprasanna Sahoo

  5. Formal Modeling and Verification of Controllers for a Family of DRAM Caches

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, November 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Debiprasanna Sahoo

  6. Work-in-Progress: DRAM Cache Access Optimization leveraging Line Locking in Tag Cache

    Article • September 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Debiprasanna Sahoo

  7. ReDRAM: A Reconfigurable DRAM Cache for GPGPUs

    Article • IEEE Computer Architecture Letters, July 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Debiprasanna Sahoo

  8. CAMO: A novel cache management organization for GPGPUs

    Article • January 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Debiprasanna Sahoo

  9. An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors

    Article • January 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Debiprasanna Sahoo

  10. MSimDRAM: Formal Model Driven Development of a DRAM Simulator

    Article • January 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Debiprasanna Sahoo