All Stories

  1. Introduction to the Special Issue on Designing Cyber-Physical Systems—From Concepts to Implementation
  2. ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
  3. A Survey of FPGA Optimization Methods for Data Center Energy Efficiency
  4. Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics
  5. Optimizing the Use of Behavioral Locking for High-Level Synthesis
  6. Iris
  7. Designing ML-resilient locking at register-transfer level
  8. Dynamically-Tunable Dataflow Architectures Based on Markov Queuing Models
  9. HOLL: Program Synthesis for Higher Order Logic Locking
  10. CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching
  11. A Survey on Domain-Specific Memory Architectures
  12. ASSURE: RTL Locking Against an Untrusted Foundry
  13. Automatic Generation of Heterogeneous SoC Architectures With Secure Communications
  14. CAD-Base
  15. TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking
  16. Black-Hat High-Level Synthesis: Myth or Reality?
  17. Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis
  18. Securing Hardware Accelerators: A New Challenge for High-Level Synthesis
  19. The Case for Polymorphic Registers in Dataflow Computing
  20. A Survey and Evaluation of FPGA High-Level Synthesis Tools
  21. Editorial
  22. An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems
  23. On the design of scalable and reusable accelerators for big data applications
  24. Scala-Based Domain-Specific Language for Creating Accelerator-Based SoCs
  25. System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip
  26. Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip
  27. Performance Estimation of Task Graphs Based on Path Profiling
  28. FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
  29. Preface
  30. PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures
  31. Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration
  32. A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces
  33. A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs
  34. Effective Reconfigurable Design: The FASTER Approach
  35. System-level memory optimization for high-level synthesis of component-based SoCs
  36. SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs
  37. Bambu: A modular framework for the high level synthesis of memory-intensive applications
  38. A framework for effective exploitation of partial reconfiguration in dataflow computing
  39. D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems
  40. Dataflow computing with Polymorphic Registers
  41. A2B: An integrated framework for designing heterogeneous and reconfigurable systems
  42. Ant Colony Optimization for mapping, scheduling and placing in reconfigurable systems
  43. Runtime adaptation on dataflow HPC platforms
  44. A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications
  45. The FASTER vision for designing dynamically reconfigurable systems
  46. A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs
  47. Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration
  48. An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs
  49. FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
  50. On the Development of a Runtime Reconfigurable Multicore System-on-Chip
  51. An open-source design and validation platform for reconfigurable systems
  52. On the automatic integration of hardware accelerators into FPGA-based embedded systems
  53. Automatic run-time manager generation for reconfigurable MPSoC architectures
  54. Smart technologies for effective reconfiguration: The FASTER approach
  55. TaBit: A framework for task graph to bitstream generation
  56. Extensions of the hArtes Tool Chain
  57. In Car Audio
  58. The hArtes Tool Chain
  59. A runtime adaptive controller for supporting hardware components with variable latency
  60. A design methodology to implement memory accesses in high-level synthesis
  61. Combined architecture and hardening techniques exploration for reliable embedded system design
  62. HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms
  63. A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells
  64. Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems
  65. Mapping and scheduling of parallel C applications with Ant Colony Optimization onto heterogeneous reconfigurable MPSoCs
  66. Performance modeling of parallel applications on MPSoCs
  67. Performance estimation for task graphs combining sequential path profiling and control dependence regions
  68. Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems
  69. HW/SW methodologies for synchronization in FPGA multiprocessors
  70. Mapping pipelined applications onto heterogeneous embedded systems
  71. Improving evolutionary exploration to area-time optimization of FPGA designs
  72. Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems
  73. High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis
  74. A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis
  75. Fitness inheritance in evolutionary and multi-objective high-level synthesis
  76. An Evolutionary Approach to Area-Time Optimization of FPGA designs