All Stories

  1. Electrically doped dynamically configurable field-effect transistor for low-power and high-performance applications

    Article • Electronics Letters, August 2015, the Institution of Engineering and Technology (the IET)

    Dr chitrakant sahu, Mr Avinash Lahgere

  2. PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET

    Article • IEEE Transactions on Electron Devices, August 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr chitrakant sahu

  3. Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

    Article • IEEE Transactions on Electron Devices, March 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr chitrakant sahu

  4. Subthreshold Analog/RF performance estimation of doping-less DGFET for ULP applications

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr chitrakant sahu

  5. Performance comparison of bulk and SOI planar junctionless SONOS memory

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr chitrakant sahu

  6. Design and performance projection of symmetric bipolar charge-plasma transistor on SOI

    Article • Electronics Letters, September 2014, the Institution of Engineering and Technology (the IET)

    Dr chitrakant sahu

  7. Device and circuit performance analysis of double gate junctionless transistors at L g = 18 nm

    Article • The Journal of Engineering, March 2014, the Institution of Engineering and Technology (the IET)

    Dr chitrakant sahu

  8. Linearly separable pattern classification using memristive crossbar circuits

    Article • March 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr chitrakant sahu

  9. Charge-Plasma Based Process Variation Immune Junctionless Transistor

    Article • IEEE Electron Device Letters, March 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr chitrakant sahu

  10. Simplified drain current model for pinch-off double gate junctionless transistor

    Article • Electronics Letters, January 2014, the Institution of Engineering and Technology (the IET)

    Dr chitrakant sahu

  11. Electrical characteristics and short channel performance comparison of different gate junctionless transistors

    Article • December 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr chitrakant sahu

  12. Characteristics of gate inside junctionless transistor with channel length and doping concentration

    Article • June 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr chitrakant sahu

  13. Investigation of ultra-thin BOX junctionless transistor at channel length of 20 nm

    Article • June 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr chitrakant sahu