All Stories

  1. SATNet: Low Complexity Encoder-Only Edge Transformer Design using Second-Order Approximation for Road Classification

    Article • IEEE Transactions on Consumer Electronics, January 2026, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  2. RENOWNED: A Real-Time Anomaly Detection and Mitigation Framework in Edge-Enabled IoV

    Article • IEEE Internet of Things Journal, June 2025, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  3. EdgeNet: Empowering Edge Device Performance by Leveraging Clustered Networks for Optimal Memory Management With Platform-Awareness

    Article • IEEE Transactions on Emerging Topics in Computational Intelligence, January 2025, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  4. QRVS: Quick and Robust Video Stitcher with Novel Single Shot Homography for Simultaneous Object Detection and Tracking

    Article • IEEE Transactions on Artificial Intelligence, January 2025, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  5. APPARENT: AI-Powered Platform Anomaly Detection in Edge Computing

    Article • IEEE Transactions on Sustainable Computing, January 2025, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  6. Cocoa-Net: Performance Analysis on Classification of Cocoa Beans Using Structural Image Feature

    Article • Informatica, September 2024, Slovenian Association Informatika

    Chandrajit Pal

  7. NIRVANA: Non-Invasive Real-Time VulnerAbility ANAlysis for RISC-V Processor

    Article • July 2024, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  8. REALITY: RL-PowEred AnomaLy Detection with Imprecise Computing in MulTi-Core SYstems

    Article • July 2024, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  9. Power and Memory Efficient High-Speed RL Based Run time Power Manager for Edge Computation

    Article • August 2023, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  10. Anomaly Behaviour tracing of CHERI-RISC V using Hardware-Software Co-design

    Article • June 2023, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  11. SqueezeNetVLAD: High-speed power and memory efficient GPS less accurate network model for visual place recognition on the edge

    Article • June 2023, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  12. Light Weight RL Based Run Time Power Management Methodology for Edge Devices

    Article • October 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  13. Clustered Network Adaptation Methodology for the Resource Constrained Platform

    Article • June 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  14. SqueezeVGGNet: A Methodology for designing low complexity VGG Architecture for Resource Constraint Edge Applications

    Article • June 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  15. A Novel Approach in WiFi CSI-Based Fall Detection

    Article • SN Computer Science, April 2022, Springer Science + Business Media

    Chandrajit Pal

  16. Fragmented Huffman-Based Compression Methodology for CNN Targeting Resource-Constrained Edge Devices

    Article • Circuits Systems and Signal Processing, February 2022, Springer Science + Business Media

    Chandrajit Pal

  17. Deep neural network for automated simultaneous intervertebral disc (IVDs) identification and segmentation of multi-modal MR images

    Article • Computer Methods and Programs in Biomedicine, June 2021, Elsevier

    Chandrajit Pal

  18. A novel deep neural design and efficient Pipeline architecture for Person Re-Identification in high resolution Video

    Article • January 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  19. Adaptive denoising of 3D volumetric MR images using local variance based estimator

    Article • Biomedical Signal Processing and Control, May 2020, Elsevier

    Chandrajit Pal

  20. Nanomagnetic logic based runtime Reconfigurable area efficient and high speed adder design methodology

    Article • Nanotechnology, February 2020, Institute of Physics Publishing

    Chandrajit Pal

  21. An Efficient Pipeline for Distant Person Detection and Identification in 4K Video using GPUs

    Article • January 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  22. Dipole coupled magnetic quantum-dot cellular automata-based efficient approximate nanomagnetic subtractor and adder design approach

    Article • Nanotechnology, October 2019, Institute of Physics Publishing

    Chandrajit Pal

  23. Nanomagnetic logic design approach for area and speed efficient adder using ferromagnetically coupled fixed input majority gate

    Article • Nanotechnology, July 2019, Institute of Physics Publishing

    Chandrajit Pal

  24. Enterprise Class Deep Neural Network Architecture for recognizing objects and faces for surveillance systems

    Article • January 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  25. Shape and Positional Anisotropy Based Area Efficient Magnetic Quantum-Dot Cellular Automata Design Methodology for Full Adder Implementation

    Article • IEEE Transactions on Nanotechnology, November 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  26. Modified Huffman based compression methodology for Deep Neural Network Implementation on Resource Constrained Mobile Platforms

    Article • May 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  27. Rician noise removal in magnitude MRI images using efficient anisotropic diffusion filtering

    Article • International Journal of Imaging Systems and Technology, August 2017, Wiley

    Chandrajit Pal

  28. Architecture for complex network measures of brain connectivity

    Article • May 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  29. An Efficient FPGA Implementation of Optimized Anisotropic Diffusion Filtering of Images

    Article • International Journal of Reconfigurable Computing, January 2016, Hindawi Publishing Corporation

    Chandrajit Pal

  30. An efficient hardware accelerated design for image denoising using Extended Trilateral filter

    Article • January 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  31. An efficient hardware design of SIFT algorithm using fault tolerant reversible logic

    Article • July 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  32. Audio de-noising by spectral subtraction technique implemented on reconfigurable hardware

    Article • August 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  33. DSP hardware software co-design of audio de-noising algorithm

    Article • January 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  34. DSP hardware design for fingerprint binarization and thinning on FPGA

    Article • January 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  35. Hardware software co-design of a fast bilateral filter in FPGA

    Article • December 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  36. Design of an FPGA based intelligence traffic light controller with VHDL

    Article • December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  37. Novel architecture of modular exponent on reconfigurable system

    Article • March 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Chandrajit Pal

  38. Design and implementation of real time secured RS232 link for multiple FPGA communication

    Article • February 2011, ACM (Association for Computing Machinery)

    Chandrajit Pal, Professor Amlan Chakrabarti, suman sau