All Stories

  1. Defect and heterometallic engineering in TiN–ZrN–HfN monolayers: A first-principles study on structural stability, electronic tunability, and optical anisotropy
  2. Metal-to-semiconductor transition and application-driven optical response of TMN armchair nanoribbons
  3. Erbium doping-induced quantum and optical enhancements in CdS: A first-principles study for optoelectronic applications
  4. Pongamia pinnata-mediated green synthesis of Er-doped CdS thin films: enhanced photocatalysis and high-efficiency optoelectronics
  5. Electronic and Magnetic Properties of Armchair and Zigzag Nanoribbons of Transition Metal Nitrides: A DFT Study
  6. A DFT Study on Armchair Nanoribbon Structures of TiN, ZrN, and HfN
  7. A DFT study on transformation of TiN's atomic chain structure into atomic chain structures of HfN and ZrN
  8. Optical property analysis of transition and alkaline metal doped MoS2 bulk layers for photo-sensor applications
  9. Structural and Electronic Property Analysis of Transition and Alkaline Metal Doped MoS2 Bulk Layers for Photo-Sensor Applications
  10. Theoretical investigation on structural transformation of TiN to HfN monolayer: A first principles study
  11. First-Principles Study on the Structural, Electronic, Optical, Mechanical, and Adsorption Properties of Cubical Transition Metal Nitrides MN (M = Ti, Zr and Hf)
  12. Mathematical Modeling of Non-Linearity due to Charge Injection Effect in CMOS Imagers
  13. Mathematical modelling of charge injection effect for CMOS image sensor and CDS circuit
  14. Clocking scheme, Reset Noise Analysis and Reduction Technique for CMOS Image Sensors utilized in Subretinal Implant
  15. Design and Analysis of Low-Power PLL for Digital Applications
  16. Progressive Development of Electrode Design Techniques and Experience with CMOS image Sensor
  17. Implementation of a novel 2-stage DFT structure for CMOS pixel sensors utilizing on-chip CP-PLL clock (for retinal implant system)
  18. An innovative approach of computational fault detection using design for testability of CP-PLL