All Stories

  1. Matrix phase detector for high bandwidth and low jitter frequency synthesis
  2. A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS
  3. 10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS
  4. Design trade-offs in ultra-low-power CMOS and STSCL digital systems
  5. Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter
  6. A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems
  7. Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits
  8. Conclusions
  9. Extreme Low-Power Mixed Signal IC Design
  10. Subthreshold Source-Coupled Logic
  11. Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems
  12. A power-efficient LVDS driver circuit in 0.18-μm CMOS technology
  13. A Low Power Base-Band Circuit for Low-IF Wireless PAN Receivers
  14. A low-power, multichannel gated oscillator-based CDR for short-haul applications