All Stories

  1. SPArch: A Hardware-oriented Sketch-based Architecture for High-speed Network Flow Measurements

    Article • ACM Transactions on Privacy and Security, August 2024, ACM (Association for Computing Machinery)

    Arish Sateesan

  2. Ultra-high-speed Bloom filter algorithms and architectures on FPGA

    Article • August 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Arish Sateesan

  3. Optimization of Convolutional Neural Networks on Resource-Constrained Devices

    Article • July 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Arish Sateesan

  4. Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier on FPGA

    Article • Circuits Systems and Signal Processing, May 2016, Springer Science + Business Media

    Arish Sateesan

  5. An efficient binary multiplier algorithm on FPGA, using Vedic mathematics.

    Article • April 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Arish Sateesan

  6. High-speed floating-point multiplier implementation on FPGA using Vedic mathematics

    Article • March 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Arish Sateesan

  7. Run-time reconfigurable multi-precision floating-point multiplier on FPGA

    Article • February 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Arish Sateesan