All Stories

  1. Rules Offload Engine (ROE): Accelerating Host SDN Policy Evaluation
  2. CoddSpeed: Hardware Accelerated Query Processing in Microsoft Fabric
  3. AI-Assisted Copilot Automation for Reliable FPGA Verification at Hyperscale
  4. Hyperscale FPGA Engineering Systems at Microsoft
  5. What To Do With Datacenter FPGAs Besides Deep Learning
  6. Introduction to MPP 2019
  7. Introduction to MPP 2018
  8. KV-Direct
  9. FPGAs in the Datacenter
  10. A Cloud-Scale Acceleration Architecture
  11. Configurable Clouds
  12. A reconfigurable fabric for accelerating large-scale datacenter services
  13. Message from the MPP 2016 Workshop Chairs
  14. A cloud-scale acceleration architecture
  15. A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services
  16. Accelerating Homomorphic Evaluation on Reconfigurable Hardware
  17. Large-scale reconfigurable computing in a microsoft datacenter
  18. A reconfigurable fabric for accelerating large-scale datacenter services
  19. Inspection-Resistant Memory Architectures
  20. How to implement effective prediction and forwarding for fusable dynamic multicore architectures
  21. Inspection resistant memory
  22. Inspection resistant memory: Architectural support for security from physical examination
  23. MPI as a Programming Model for High-Performance Reconfigurable Computers
  24. Performance and power of cache-based reconfigurable computing
  25. MPI as an abstraction for software-hardware interaction for HPRCs
  26. CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures
  27. The WaveScalar architecture
  28. Instruction scheduling for a tiled dataflow architecture
  29. Area-Performance Trade-offs in Tiled Dataflow Architectures
  30. Instruction scheduling for a tiled dataflow architecture
  31. Modeling instruction placement on a spatial architecture
  32. Reducing control overhead in dataflow architectures