All Stories

  1. Dynamic behavior of a smart device on a surface subjected to earthquake motion
  2. Modeling and Analysis of Passive Switching Crossbar Arrays
  3. Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches
  4. The Feasibility of Using Smart Devices for Quantifying Seismic Damage to Buildings
  5. A Simple Full-Duplex MAC Protocol Exploiting Asymmetric Traffic Loads in WiFi Systems
  6. A case study to develop a graduate-level degree program in embedded & cyber-physical systems
  7. On the Optimum Data Carrier for Intra-body Communication Applications
  8. A Dynamic and Collaborative Truck Appointment Management System in Container Terminals
  9. Process variations-aware resistive associative processor design
  10. A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints
  11. Simulating Two-Dimensional Stick-Slip Motion of a Rigid Body using a New Friction Model
  12. Dynamic Resource Management in High Throughput Satellite with Multi Port Amplifier (MPA)
  13. A Simulation Based Study Of The Effect Of Truck Arrival Patterns On Truck Turn Time In Container Terminals
  14. Poster Abstract: Unifying Modeling Substrate for Irrigation Cyber-Physical Systems
  15. Performance analysis of full-duplex multiuser decode-and-forward relay networks with interference management
  16. Microarchitecture-Level SoC Design
  17. Erratum to: Chapter 4 Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance
  18. Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance
  19. DWT-based watermarking technique for video authentication
  20. Intra-body communication model based on variable biological parameters
  21. A cortical activity localization approach for decoding finger movements from human electrocorticogram signal
  22. Full-Duplex Systems Using Multireconfigurable Antennas
  23. All-Digital Self-Interference Cancellation Technique for Full-Duplex Systems
  24. On Phase Noise Suppression in Full-Duplex Systems
  25. Advanced base station precoding and user receiver designs for LTE-Advanced networks
  26. A Beam-Steering Reconfigurable Antenna for WLAN Applications
  27. An interference cancellation strategy for broadcast in hierarchical cell structure
  28. High SNR Linear Estimation of Vector Sources
  29. Distributed detection for wireless sensor networks with fusion center under correlated noise
  30. Decentralized Estimation Under Correlated Noise
  31. Multicopy Cache
  32. State dependent statistical timing model for voltage scaled circuits
  33. Low power reduced-complexity error-resilient MIMO detector
  34. Self-interference cancellation with phase noise induced ICI suppression for full-duplex systems
  35. Low overhead correction scheme for unreliable LDPC buffering
  36. Self-interference cancellation with nonlinear distortion suppression for full-duplex systems
  37. Error-aware power management for memory dominated OFDM systems
  38. MPMAP : A high level synthesis and mapping tool for MPSoCs
  39. Rate Gain Region and Design Tradeoffs for Full-Duplex Wireless Communications
  40. Heterogeneous memory management for 3D-DRAM and external DRAM with QoS
  41. Error resilient MIMO detector for memory-dominated wireless communication systems
  42. Session MA6b: DSP Architecture for wireless communications (invited) [breaker page]
  43. Reliable low power Distributed Arithmetic filters via N-Modular Redundancy
  44. Linear Decentralized Estimation of Correlated Data for Power-Constrained Wireless Sensor Networks
  45. Fast error aware model for arithmetic and logic circuits
  46. Joint Detection and Decoding for MIMO Systems Using Convolutional Codes: Algorithm and VLSI Architecture
  47. A Best-First Soft/Hard Decision Tree Searching MIMO Decoder for a 4 $\times$ 4 64-QAM System
  48. Linear Estimation of Correlated Vector Sources for Wireless Sensor Networks with Fusion Center
  49. Simultaneous transmit and sense for cognitive radios using full-duplex: A first study
  50. Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications
  51. Multiuser communications using beam-tilting antennas
  52. Optimized scheduling algorithm for LTE downlink system
  53. Spectral efficiency and energy consumption tradeoffs for reconfigurable devices in heterogeneous wireless systems
  54. Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling
  55. History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring
  56. Area, reconfiguration delay and reliability trade-offs in designing reliable multi-mode FIR filters
  57. Adjustable supply voltages and refresh cycle for process variations, temperature changes, and device degradation adaptation in 1T1C embedded DRAM
  58. A Class of Low Power Error Compensation Iterative Decoders
  59. Energy aware task mapping algorithm for heterogeneous MPSoC based architectures
  60. Embedded Memories Fault-Tolerant Pre- and Post-Silicon Optimization
  61. Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation
  62. Using Reconfigurable Devices to Maximize Spectral Efficiency in Future Heterogeneous Wireless Systems
  63. Multiuser Sum MSE Minimization Relaying Strategy
  64. Amplify-and-Forward Relay Networks under Received Power Constraint with Imperfect CSI
  65. Linear decentralized estimation of correlated data for wireless sensor networks
  66. Adjustable supply voltages and refresh cycle for process variations and temperature changing adaptation in DRAM to minimize power consumption
  67. FFT processing through faulty memories in OFDM based systems
  68. A Unified Hardware and Channel Noise Model for Communication Systems
  69. Reduced Overhead Training for Multi Reconfigurable Antennas with Beam-Tilting Capability
  70. A combined channel and hardware noise resilient Viterbi decoder
  71. Design and Implementation of a Sort-Free K-Best Sphere Decoder
  72. Cognitive Radio Rides on the Cloud
  73. Process variation aware transcoding for low power H.264 decoding
  74. A Radius Adaptive K-Best Decoder With Early Termination: Algorithm and VLSI Architecture
  75. EVALUATION FRAMEWORK FOR K-BEST SPHERE DECODERS
  76. Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters
  77. A best-first tree-searching approach for ML decoding in MIMO system
  78. Effect of body biasing on embedded SRAM failure
  79. Low-Power Multimedia System Design by Aggressive Voltage Scaling
  80. An Adaptive Reduced Complexity K-Best Decoding Algorithm with Early Termination
  81. Placement-aware partial reconfiguration for a class of FIR-like structures
  82. E < MC2
  83. Amplify-and-Forward Relay Networks Under Received Power Constraint
  84. Design and Implementation of a Scalable Channel Emulator for Wideband MIMO Systems
  85. Architectural Optimizations for Low-Power $K$ -Best MIMO Decoders
  86. A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment
  87. Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling
  88. A fault tolerant cache architecture for sub 500mV operation
  89. Link Performance Improvement Using Reconfigurable Multiantenna Systems
  90. Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems
  91. On the VLSI Implementation of low complexity K-best MIMO decoders
  92. Cross-layer co-exploration of exploiting error resilience for video over wireless applications
  93. Optimizations of a MIMO Relay Network
  94. Managing leakage power and reliability in hot chips using system floorplanning and SRAM design
  95. A partial memory protection scheme for higher effective yield of embedded memory for video data
  96. Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices
  97. Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips
  98. On Channel Estimation and Capacity for Amplify and Forward Relay Networks
  99. Joint Power Loading of Data and Pilots in OFDM Using Imperfect Channel State Information at the Transmitter
  100. On Signal Processing Methods for MIMO Relay Architectures
  101. Power Management for Cognitive Radio Platforms
  102. Limits on voltage scaling for caches utilizing fault tolerant techniques
  103. Error-Aware Design
  104. A Scalable Wireless Channel Emulator for Broadband MIMO Systems
  105. Simulation, implementation and performance evaluation of a diversity enabled WCDMA mobile terminal
  106. Fault Tolerant Approaches Targeting Ultra Low Power Communications System Design
  107. Cross Layer Error Exploitation for Aggressive Voltage Scaling
  108. Design and Implementation of a Baseband WCDMA Dual-Antenna Mobile Terminal
  109. Exploiting Fault Tolerance Towards Power Efficient Wireless Multimedia Applications
  110. A Real-Time Wireless Channel Emulator for MIMO Systems
  111. System Redundancy; A Means of Improving Process Variation Yield Degradation in Memory Arrays
  112. Implementation of a carrier frequency recovery loop for MIMO-CDMA systems
  113. Improving effective yield through error tolerant system design
  114. Design and VLSI Implementation for a WCDMA Multipath Searcher
  115. Wireless field trial results of a high hopping rate FHSS-FSK testbed
  116. A low-power DS-CDMA RAKE receiver utilizing resource allocation techniques
  117. Collision of vehicles with bridge piers
  118. Modified all digital timing tracking loop for wireless applications
  119. Integrated Circuit Technologies for Wireless Communications
  120. System-Level SRAM Yield Enhancement
  121. Interpolation based direct digital frequency synthesis for wireless communications
  122. Piece-wise parabolic interpolation for direct digital frequency synthesis
  123. A novel multipath searcher implementation for WCDMA receivers
  124. Diversity processing WCDMA cell searcher implementation
  125. Implementation of a digital timing recovery circuit for CDMA applications
  126. An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories
  127. A low-power ASIC implementation of 2Mbps antenna-rake combiner for WCDMA with MRC and LMS capabilities
  128. Dual antenna UMTS mobile station transceiver ASIC for 2 Mb/s data rate