All Stories

  1. Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

    Article • International Journal of Circuit Theory and Applications, April 2020, Wiley

    ADITYA JAPA, Dr Manoj Kumar Majumder

  2. A Low Area Overhead DPA Countermeasure Exploiting Tunnel Transistor based Random Number Generator

    Article • IET Circuits Devices & Systems, March 2020, the Institution of Engineering and Technology (the IET)

    ADITYA JAPA, Dr Manoj Kumar Majumder

  3. Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks

    Article • IET Circuits Devices & Systems, August 2019, the Institution of Engineering and Technology (the IET)

    ADITYA JAPA, Dr Manoj Kumar Majumder

  4. Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities

    Article • May 2018, Institute of Electrical & Electronics Engineers (IEEE)

    ADITYA JAPA

  5. Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs

    Article • January 2017, Springer Science + Business Media

    ADITYA JAPA

  6. Exploiting the steep subthreshold slope characteristics of tunnel transistors for wide tuning range voltage controlled ring oscillator (VCRO) design at scaled supply voltages down to 150mV

    Article • December 2016, Institute of Electrical & Electronics Engineers (IEEE)

    ADITYA JAPA

  7. Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction

    Article • IET Circuits Devices & Systems, November 2016, the Institution of Engineering and Technology (the IET)

    ADITYA JAPA