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  1. Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication

    Article • June 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Adarsh Patil

  2. Cache management techniques for an integrated CPU+GPU processor with die stacked DRAM

    Article • ACM Transactions on Architecture and Code Optimization, December 2017, ACM (Association for Computing Machinery)

    Adarsh Patil