All Stories

  1. On SFC Low Power Hardware Implementation in FPGAs
  2. Multiple-Core PLC CPU Implementation and Programming
  3. Hardware Mapping Strategies of PLC Programs in FPGAs
  4. Technology mapping of multi-output function into LUT-based FPGA
  5. Nonlinearity Measurement of a Voltage Ramp Using a Digital Technique
  6. Multiple core PLC CPU with tight thread synchronization
  7. On hardware synthesis and implementation of PLC programs in FPGAs
  8. Efficient implementation of PLC programs by partitioning
  9. Distributed PLC Based on Multicore CPUs - Architecture and Programming
  10. High Level Model of Time Predictable Multitask Control Unit
  11. On PLCs Control Program Hardware Implementation Selected Problems of Mapping and Scheduling
  12. On Ladder Diagrams Compilation and Synthesis to FPGA Implemented Reconfigurable Logic Controller
  13. Synteza i implementacja uk�adu sterowania w strukturze FPGA opisanego j�zykiem SFC zgodnego z IEC61131
  14. Introducing fuzzy default logic into WalkSAT algorithm
  15. On FPGA dedicated SFC synthesis and implementation according to IEC61131
  16. On Translation of LD, IL and SFC Given According to IEC-61131 for Hardware Synthesis of Reconfigurable Logic Controller
  17. On Hardware Synthesis of Reconfigurable Logic Controllers From Ladder Diagrams According to IEC61131-3
  18. Synthesis and Implementation of Reconfigurable PLC on FPGA Platform
  19. Dynamic Rescheduling of Tasks in Time Predictable Embedded Systems
  20. Measurement Aspects of Genome Pattern Investigations - Hardware Implementation
  21. Hardware Implementation of Fuzzy Default Logic
  22. Automatic implementation of arithmetic operation in reconfigurable logic controllers
  23. An Efficient Hardware Implementation of Smith-Waterman Algorithm Based on the Incremental Approach
  24. Central Processing Units for PLC implementation in Virtex-4 FPGA
  25. Hardware model of commonsense reasoning based on Fuzzy Default Logic
  26. Logic synthesis based on decomposition for CPLDs
  27. On Efficient Implementation of Search Algorithm for Genome Patterns
  28. Multithread RISC architecture based on programmable interleaved pipelining
  29. Programmable Logic Controller based on reconfigurable logic
  30. The Reconfigurable Hardware Accelerator for Searching Genome Patterns
  31. VEST - An intelligent tool for timing SoCs verification using UML timing diagrams
  32. Complex mathematical models simulation on mixed HDL-simulink platform
  33. A new hardware algorithm for searching genome patterns
  34. Block party [system modelling]
  35. HDL Simulation and mathematical modelling integration
  36. High level synthesis - reconfigurable hardware implementation of programmable logic controller
  37. COMPACT PLC WITH EVENT-DRIVEN PROGRAM TASKS EXECUTION
  38. REMARKS ON IMPROVING OF OPERATION SPEED OF THE PLCs
  39. TOOLS AND TECHNOLOGIES FOR DESIGNING CONTROL SYSTEMS USING PROGRAMMABLE LOGIC DEVICES
  40. A novel method of two-stage decomposition dedicated for PAL-based CPLDs
  41. B03: High speed arithmetic calculation unit for Xilinx type FPGAs
  42. Software Industrial Controller - “soft PLC”
  43. Accelerated Co-Simulation of Hardware-Software System Based on Configurable Hardware Accelertor and Selective Simulation
  44. PID Module for Reconfigurable Logic Controller
  45. Decomposition of Multi-Output Functions for CPLDs