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  1. Design of synchronous reference frame phase-locked loop with the presence of dc offsets in the input voltage

    Article • IET Power Electronics, December 2015, the Institution of Engineering and Technology (the IET)

    Mr Abhijit Kulkarni

  2. Analysis of Bandwidth–Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions

    Article • IEEE Transactions on Industrial Electronics, December 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Mr Abhijit Kulkarni