All Stories

  1. Post-Quantum Cryptography for Quantum Resilient Data Transfer

    Article • July 2025, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  2. LEARNING OBJECTS IN UNIVERSITY TEACHING OF BASIC NATURAL SCIENCE SUBJECTS

    Article • June 2025, IATED Academy, S.L.

    PhD José L Imaña

  3. ARM Architecture Optimizations for Line-Rate PQC Communications

    Article • May 2025, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  4. First Demonstration of 200 Gbps Regime Line-Rate Quantum-Secure MACsec Optical Links Using Commodity Hardware Offloads

    Article • January 2025, Optical Society of America (OSA)

    PhD José L Imaña

  5. Low-Complexity Hardware Architecture of APN Permutations Using TU-Decomposition

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, December 2024, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  6. Integrating Post-Quantum Cryptography Plugins for IPsec Offloads to Data Processing Units in the Cloud-Edge Continuum

    Article • October 2024, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  7. In-line rate encrypted links using pre-shared post-quantum keys and DPUs

    Article • Scientific Reports, September 2024, Springer Science + Business Media

    PhD José L Imaña

  8. Wireless and Fiber-Based Post-Quantum-Cryptography-Secured IPsec Tunnel

    Article • Future Internet, August 2024, MDPI AG

    PhD José L Imaña

  9. Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, August 2024, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  10. The zero-tax data center: a use case through quantum resilient communications

    Article • July 2024, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  11. Falcon/Kyber and Dilithium/Kyber Network Stack on Nvidia’s Data Processing Unit Platform

    Article • IEEE Access, January 2024, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  12. First Line-rate End-to-End Post-Quantum Encrypted Optical Fiber Link Using Data Processing Units (DPUs)

    Article • January 2024, Optical Society of America (OSA)

    PhD José L Imaña

  13. Hardware architecture of Dillon’s APN permutation for different primitive polynomials

    Article • Microprocessors and Microsystems, November 2023, Elsevier

    PhD José L Imaña

  14. Domain-oriented masked bit-parallel finite-field multiplier against side-channel attacks

    Article • Information Processing Letters, August 2023, Elsevier

    PhD José L Imaña

  15. INTERACTIVE RESOURCES TO ENHANCE SELF-LEARNING IN HIGHER EDUCATION

    Article • July 2023, IATED Academy, S.L.

    V. María Barragán, PhD José L Imaña

  16. Decomposition of Dillon’s APN Permutation with Efficient Hardware Implementation

    Article • January 2023, Springer Science + Business Media

    PhD José L Imaña

  17. Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography

    Article • October 2022, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  18. Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, August 2022, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  19. Low-Delay FPGA-Based Implementation of Finite Field Multipliers

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, August 2021, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  20. Efficient Hardware Implementation of Finite Field Arithmetic AB+C for Binary Ring-LWE Based Post-Quantum Cryptography

    Article • IEEE Transactions on Emerging Topics in Computing, January 2021, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  21. Optimized reversible quantum circuits for $${\mathbb {F}}_{2^8}$$ multiplication

    Article • Quantum Information Processing, January 2021, Springer Science + Business Media

    PhD José L Imaña

  22. High-throughput architecture for post-quantum DME cryptosystem

    Article • Integration, November 2020, Elsevier

    PhD José L Imaña

  23. FPGA Implementation of Post-Quantum DME Cryptosystem

    Article • May 2020, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  24. LFSR-based Bit-Serial $GF(2^m)$ Multipliers using Irreducible Trinomials

    Article • IEEE Transactions on Computers, January 2020, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  25. Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials

    Article • IEEE Transactions on Computers, June 2018, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  26. Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials

    Article • April 2018, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  27. Reconfigurable implementation of GF(2m) bit-parallel multipliers

    Article • March 2018, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  28. Low-delay AES polynomial basis multiplier

    Article • Electronics Letters, May 2016, the Institution of Engineering and Technology (the IET)

    PhD José L Imaña

  29. High-Speed Polynomial Basis Multipliers Over GF(2m) for Special Pentanomials

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, January 2016, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  30. Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials

    Article • Integration, March 2013, Elsevier

    PhD José L Imaña

  31. Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations

    Article • IEEE Industrial Electronics Magazine, January 2013, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  32. Efficient Polynomial Basis Multipliers for Type-II Irreducible Pentanomials

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, November 2012, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  33. Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation

    Article • IEEE Industrial Electronics Magazine, July 2011, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  34. Low Latency $GF(2^{m})$ Polynomial Basis Multiplier

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, May 2011, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  35. Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation

    Article • August 2010, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  36. Probabilistic Verification over GF(2m) Using Mod2-OBDDs

    Article • Intelligent Information Management, January 2010, Scientific Research Publishing, Inc,

    PhD José L Imaña

  37. Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, December 2006, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  38. Finite Fields: Applications and Implementations – Guest Editorial

    Article • Acta Applicandae Mathematicae, September 2006, Springer Science + Business Media

    PhD José L Imaña

  39. Bit-parallel finite field multipliers for irreducible trinomials

    Article • IEEE Transactions on Computers, May 2006, Institute of Electrical & Electronics Engineers (IEEE)

    PhD José L Imaña

  40. Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2 m ) Generated by AOPs

    Article • The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, February 2006, Springer Science + Business Media

    PhD José L Imaña

  41. Streaming potential across cation-exchange membranes in methanol–water electrolyte solutions

    Article • Journal of Colloid and Interface Science, February 2006, Elsevier

    PhD José L Imaña, V. María Barragán

  42. A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2m)

    Article • January 2003, Springer Science + Business Media

    PhD José L Imaña

  43. Effect of an AC perturbation on a desalination electrodialysis process

    Article • Desalination, March 2002, Elsevier

    PhD José L Imaña, V. María Barragán

  44. Article • Acta Applicandae Mathematicae, January 2002, Springer Science + Business Media

    PhD José L Imaña

  45. Formulation for the computation of Boolean operations

    Article • IEE Proceedings - Computers and Digital Techniques, November 2001, the Institution of Engineering and Technology (the IET)

    PhD José L Imaña