All Stories

  1. A Perspective on the Topics from a Selection of Papers from the First Twenty Years of the International Symposium on Applied Reconfigurable Computing (ARC)
  2. A flexible task graph for any C application
  3. A CPU-FPGA Holistic Source-To-Source Compilation Approach for Partitioning and Optimizing C/C++ Applications
  4. A Study on Hyperparameters Configurations for an Efficient Human Activity Recognition System
  5. A methodology and framework for software memoization of functions
  6. Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey
  7. Compiler Techniques for Efficient MATLAB to OpenCL Code Generation
  8. Introduction to the Special Section on FPL 2015
  9. The First 25 Years of the FPL Conference
  10. Foreword to the special issue of the 18th IEEE international conference on computational science and engineering (CSE2015)
  11. SSA-based MATLAB-to-C compilation and optimization
  12. The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems
  13. A MATLAB subset to C compiler targeting embedded systems
  14. Clustering-Based Selection for the Exploration of Compiler Optimization Sequences
  15. Guest Editorial ARC 2014
  16. Techniques for efficient MATLAB-to-C compilation
  17. Guest Editorial FPL 2013
  18. C and OpenCL generation from MATLAB
  19. Transparent Acceleration of Program Execution using Reconfigurable Hardware
  20. Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach
  21. Enabling FPGA routing configuration sharing in dynamic partial reconfiguration
  22. Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
  23. A clustering-based approach for exploring sequences of compiler optimizations
  24. Exploration of compiler optimization sequences using clustering-based selection
  25. High-Level Synthesis from C vs. a DSL-Based Approach
  26. Reconfigurable Computing: Architectures, Tools, and Applications
  27. Multi-Target C Code Generation from MATLAB
  28. Coarse/Fine-grained Approaches for Pipelining Computing Stages in FPGA-Based Multicore Architectures
  29. Exploration of compiler optimization sequences using clustering-based selection
  30. General chair message
  31. Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
  32. Enriching MATLAB with aspect-oriented features for developing embedded systems
  33. The MATISSE MATLAB compiler
  34. Related Work
  35. Introduction
  36. Compilation and Synthesis for Embedded Reconfigurable Systems
  37. The LARA Language
  38. Conclusions
  39. Architecture for Transparent Binary Acceleration of Loops with Memory Accesses
  40. Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
  41. LARA Experiments
  42. An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits
  43. An FPGA-based multi-core approach for pipelining computing stages
  44. The REFLECT Design-Flow
  45. Resource-Efficient Designs Using an Aspect-Oriented Approach
  46. Controlling Hardware Synthesis with Aspects
  47. Hardware pipelining of runtime-detected loops
  48. Programming strategies for runtime adaptability
  49. Hardware/software specialization through aspects: The LARA approach
  50. Analysis of error detection schemes: Toolchain support and hardware/software implications
  51. Specifying Compiler Strategies for FPGA-based Systems
  52. LARA
  53. Program and Aspect Metrics for MATLAB
  54. Experiments with the LARA aspect-oriented approach
  55. From Instruction Traces to Specialized Reconfigurable Arrays
  56. Techniques for Dynamically Mapping Computations to Coprocessors
  57. Identifying Merge-Beneficial Software Kernels for Hardware Implementation
  58. LALP: A Language to Program Custom FPGA-Based Acceleration Engines
  59. A Domain-Specific Language for the Specification of Adaptable Context Inference
  60. Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks
  61. Programming safety requirements in the REFLECT design flow
  62. Reconfigurable Computing
  63. Conclusion
  64. Introduction
  65. Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)
  66. Code Transformations for Embedded Reconfigurable Computing Architectures
  67. REFLECT: Rendering FPGAs to Multi-core Embedded Computing
  68. On identifying and optimizing instruction sequences for dynamic compilation
  69. A Query Processing Strategy for Conceptual Queries Based on Object-Role Modeling
  70. On Identifying Segments of Traces for Dynamic Compilation
  71. On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates
  72. On using LALP to map an audio encoder/decoder on FPGAs
  73. Compiling for reconfigurable computing
  74. Providing user context for mobile and social networking applications
  75. Welcome message
  76. Preprocessing techniques for context recognition from accelerometer data
  77. Unbalanced FIFO sorting for FPGA-based systems
  78. A comparison of three representative hardware sorting units
  79. LALP: A Novel Language to Program Custom FPGA-Based Architectures
  80. Automatic generation of FPGA hardware accelerators using a domain specific language
  81. Compilation Techniques for Reconfigurable Architectures
  82. The current feasibility of gesture recognition for a smartphone using J2ME
  83. An Analysis of Navigation Algorithms for Smartphones Using J2ME
  84. Mobile Context Provider for Social Networking
  85. Synthesis of regular expressions for FPGAs
  86. IJE special issue on reconfigurable hardware systems
  87. Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures
  88. Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures
  89. Introduction
  90. Compilers for Reconfigurable Architectures
  91. Overview of Reconfigurable Architectures
  92. Final Remarks
  93. Code Transformations
  94. Compilation and Synthesis Flows
  95. Mapping and Execution Optimizations
  96. Perspectives on Programming Reconfigurable Computing Platforms
  97. Regular Expression Matching in Reconfigurable Hardware
  98. Aggressive Loop Pipelining for Reconfigurable Architectures
  99. An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics
  100. On Adapting Power Estimation Models for Embedded Soft-Core Processors
  101. A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops
  102. Reconfigurable Computing: Architectures, Tools and Applications
  103. A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures
  104. Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements
  105. A Methodology to Design FPGA-based PID Controllers
  106. Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures
  107. Reconfigurable Computing: Architectures and Applications
  108. New challenges in computer science education
  109. Dynamic loop pipelining in data-driven architectures
  110. New challenges in computer science education
  111. Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping
  112. Self-loop Pipelining and Reconfigurable Dataflow Arrays
  113. Modeling Loop Unrolling: Approaches and Open Issues
  114. An Environment for Exploring Data-Driven Architectures
  115. XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
  116. Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
  117. An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs
  118. Architectures and compilers to support reconfigurable computing
  119. Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture
  120. Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues
  121. The Role of Programming Models on Reconfigurable Computing Fabrics